Workshop CAPITAL 2022 : sCalable And PrecIse Timing AnaLysis for multicore platforms

 WORKSHOP CAPITAL : sCalable And PrecIse Timing AnaLysis for multicore platforms

Friday, June 3th, 2022. Grenoble and possible remote attendance


Renato Mancuso, Boston University "From Memory Partitioning to Management through Fine-grained Profiling and Control."

 Invited Speakers

  • Hai Nam Tran, Lab-STICC - Université de Bretagne Occidentale, Brest, France

Memory hierarchy in scheduling simulation : problems, implementation & return of experience

  • Ignacio Sañudo Olmedo, Università degli studi di Modena e Reggio Emilia

An historical view of scheduling and resource management problems using NVIDIA GPUs in safety related domains

  • Julien Forget, CRIStAL, Université de Lille, France

Code generation for multi-phase tasks on a multi-core distributed memory platform

  • Daniel Casini, Scuola Superiore Sant’Anna, Pisa, Italy

Autonomous-driving frameworks and predictability : challenges and open problems

  • Patricia Balbastre ** (Universitat Politècnica de València, Valencia, Spain)

Interference modelling and analysis in hard real-time multiprocessor systems

 General Topic of CAPITAL :

The design and the implementation of time-critical applications upon multi-core processors are considered. Multi-core processors have the potential to offer high computing power. Unfortunately, their extensive use of shared resources (e.g.,caches, DRAM, buses, etc.) makes the design and the implementation difficult to predict — especially in situations where hard real-time constraints must be satisfied. Recent works show that an important challenge is to design a precise and scalable timing analysis. To address this challenge the research community consider closely both sides of the system : software and hardware. The aim of this co-design approach is therefore to guarantee scalability, precision and low complexity of the solution without compromising flexible efficient use of resources. The solution must be tailored for the target application and platform. In particular by identifying the shared resources (memory, bus, cache) and by reducing the complexity based on interference delay using, for instance, a tailored mapping/scheduling, bandwidth regulator. The solution must be also based on a good use of the hardware architecture (memory banks, cache, communication media) with techniques like physical/temporal partitioning to obtain a precise solution.


  • Thomas Carle (IRIT, Université de Toulouse, France)
  • Joël Goossens (ULB, Brussels, Belgium)
  • Claire Maiza (Grenoble INP/Ensimag, Verimag, Grenoble, France)
  • Juan M Rivas (Universidad de Cantabria, Santander, Spain)

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