Friday, June 3th, 2022. Grenoble, bâtiment IMAG; and possible remote attendance
Free attendance. Registration is close but do not hesitate to contact Claire Maiza in case you still would like to attend.
Renato Mancuso, Boston University
- Hai Nam Tran, Lab-STICC - Université de Bretagne Occidentale, Brest, France
- "Memory hierarchy in scheduling simulation : problems, implementation & return of experience"
- Alessio Masola, Università degli studi di Modena e Reggio Emilia
- "Understanding memory interference in CPU-GPU embedded systems"
- Julien Forget, CRIStAL, Université de Lille, France
- "Code generation for multi-phase tasks on a multi-core distributed memory platform"
- Daniel Casini, Scuola Superiore Sant’Anna, Pisa, Italy
- "Autonomous-driving frameworks and predictability: challenges and open problems"
- Patricia Balbastre ** (Universitat Politècnica de València, Valencia, Spain)
- "Interference modelling and analysis in hard real-time multiprocessor systems"
- 9.00 Welcome
- 9.15 Keynote
- 10.15 break
- 10.45 Invited talks
- 12.30 lunch break
- 13.30 Invited talks 2
- 16.15 Panel Discussion
- 16.45 Closing
The design and the implementation of time-critical applications upon multi-core processors are considered. Multi-core processors have the potential to offer high computing power. Unfortunately, their extensive use of shared resources (e.g.,caches, DRAM, buses, etc.) makes the design and the implementation difficult to predict — especially in situations where hard real-time constraints must be satisfied. Recent works show that an important challenge is to design a precise and scalable timing analysis. To address this challenge the research community consider closely both sides of the system: software and hardware. The aim of this co-design approach is therefore to guarantee scalability, precision and low complexity of the solution without compromising flexible efficient use of resources. The solution must be tailored for the target application and platform. In particular by identifying the shared resources (memory, bus, cache) and by reducing the complexity based on interference delay using, for instance, a tailored mapping/scheduling, bandwidth regulator. The solution must be also based on a good use of the hardware architecture (memory banks, cache, communication media) with techniques like physical/temporal partitioning to obtain a precise solution.
- Thomas Carle (IRIT, Université de Toulouse, France)
- Joël Goossens (ULB, Brussels, Belgium)
- Claire Maiza (Grenoble INP/Ensimag, Verimag, Grenoble, France)
- Juan M Rivas (Universidad de Cantabria, Santander, Spain)
The workshop is partially funded by: UGA/GrenobleINP and