26ème Workshop sur la programmation Synchrone, à Aussois, du 25 au 29 Novembre 2019
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Verimag
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Colloques et Conférences
- 20 ans de Verimag, 26-28 (...)
- École d’été PERSYVAL-Lab sur (...)
- ACES’2008 September 29th, (...)
- ADSL 2018
- ADSL 2020 (@POPL 2020)
- AlgoTel 2017
- AlgoTel et CoRes 2020
- ARCH14
- ARTIST Summer School in (...)
- ARTIST2 Summer School 2008 in
- ASL 2022 : Advances in (...)
- AVM 2014
- AVoCS 2019
- BEeSy 2015
- CAPITAL Workshop - sCalable
- CAS 2012, January 13, Grenoble
- CAV 2009 June 26 - July (...)
- EMSOFT 2009 October 12 - (...)
- ETAPS 2014
- Euro-Par 2016
- FAC 2014
- FIMCP 2013, May 2nd, Marrakech
- FORMATS 2014
- FORMATS 2015
- GreHack 2016
- GT Verif 2018
- HSB 2014
- HSCC 2012, Apr 17-19, Beijing
- ICDCN 2012, January 3-6, (...)
- IWHSB 2013
- Journée informatique frugale
- MEMOCODE 2010, July 26-28,
- MEMOCODE 2011, July 11-13,
- MeTRiD 2018
- MOVEP 2020
- RESSI 2017
- RTNS 2017
- RV 2018
- SSS 2020
- SSS’2011, October 10-12, (...)
- SSS’2016
- Synchron 2019
- SynCoP 2014
- Toward Systems Biology (...)
- VECoS 2018
- VVS
- WCET 2013, July 9, 2013, (...)
- WFAC’2008 - October 19th, (...)
- Workshop CAPITAL
- Workshop CAPITAL 2022 : (...)
- Workshop on Timing Anomalies
- RESSI 2017 : les Rendez-vous
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Actualités
Séminaires
Nouvelles publications
- Quelques Publications
Récentes
- Abdelhakim Baouya, Samir Ouchani, Saddek Bensalem: Formal Modelling and Security Analysis of Inter-Operable Systems
- David Monniaux, Sylvain Boulmé: The Trusted Computing Base of the CompCert Verified Compiler
- Karine Altisen, Stéphane Devismes, Erwan Jahier: sasa: a SimulAtor of Self-stabilizing Algorithms
- David Monniaux, Léo Gourdin, Sylvain Boulmé, Olivier Lebeltel: Testing a Formally Verified Compiler
Offres d'emploi et stages
- Offres d'emploi et stages
- [Master] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
- Bourses PERSYVAL de M2
- [Master] Modélisation et caractérisation d’attaques par faute exploitant l’architecture mémoire
- [Master] Compilation prouvée sécurisée vers processeur RISC-V
- [Master] A Solver for Monadic Second Order Logic of Graphs of Bounded Tree-width
- [Master] Analyzing fault parameters triggering timing anomalies
- [Master] Exploration by model-checking of timing anomaly cancellation in a processor
- [Master] Formal Methods for the Verification of Self-Adapting Distributed Systems
- [Master] Modeling and Simulation of Modular Robots with DR-BIP
- [Master] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
- [Master]Leakage in presence of an active and adaptive adversary
- [PhD] Logical Foundations of Self-Adapting Distributed Systems
- [PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
