CAPITAL Workshop - sCalable And PrecIse Timing AnaLysis for multicore platforms

Webinar. June, 4th. 1pm CET.

 WORKSHOP CAPITAL: sCalable And PrecIse Timing AnaLysis for multicore platforms

Friday, June 4th, 2021. 1pm CET. Webinar.

Free access, Registration Form



  • 13.00 CET: Keynote Talk By Sébastien Faucou (Université de Nantes, CNRS, LS2N) "Formal models of timed systems: WCET analysis in single-core systems, and some ideas for timing analysis in multi-core systems"
  • 14.00 Junior presentations
  • 14.30 Break
  • 14.45 Emmanuel Grolleau (LIAS, ENSMA, University of Poitiers), "Global scheduling on heterogeneous MPSoCs".
  • 15.15 Eric Jenn (IRT Saint Exupéry), "A long and winding road towards predictability …".
  • 15.45 Break
  • 16.00 Angeliki Kritikakou (University of Rennes, INRIA, IRISA, CNRS), "Run-time adaptation of task execution in time-critical systems: Challenges and Solutions".
  • 16.30 Geoffrey Nelissen (Eindhoven University of Technology), "Schedulability analysis based on schedule abstraction graphs: status, limitations and future work".
  • 17.00-17.30 Panel discussion

Workshop registration form

 General Topic of CAPITAL:

The design and the implementation of time-critical applications upon multi-core processors are considered. Multi-core processors have the potential to offer high computing power. Unfortunately, their extensive use of shared resources (e.g.,caches, DRAM, buses, etc.) makes the design and the implementation difficult to predict — especially in situations where hard real-time constraints must be satisfied. Recent works show that an important challenge is to design a precise and scalable timing analysis. To address this challenge the research community consider closely both sides of the system: software and hardware. The aim of this co-design approach is therefore to guarantee scalability, precision and low complexity of the solution without compromising flexible efficient use of resources. The solution must be tailored for the target application and platform. In particular by identifying the shared resources (memory, bus, cache) and by reducing the complexity based on interference delay using, for instance, a tailored mapping/scheduling, bandwidth regulator. The solution must be also based on a good use of the hardware architecture (memory banks, cache, communication media) with techniques like physical/temporal partitioning to obtain a precise solution.


  • Joël Goossens (ULB, Brussels, Belgium)
  • Claire Maiza (Grenoble INP/Ensimag, Verimag, Grenoble, France)
  • Juan M Rivas (Universidad de Cantabria, Santander, Spain)

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