1st International Workshop on Model Based Architecting and Construction of Embedded Systems, ACES’2008 September 29th, 2008 Toulouse, France (in conjunction with MODELS 2008)
ACES’2008 September 29th, 2008 Toulouse, France
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- 20 years of Verimag, September
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Seminars
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- 7 November 2024 Aurèle Barrière: Formal verification beyond traditional compilation
- 21 November 2024 Chao Huang: : safe reinforcement learning with verification in the loss
- 28 November 2024 Grégoire Bussone: Tba (synchronous language compilers: translation validation and optimizations)
- 2 December 2024 Thomas Vigouroux: Quantitative analysis for adaptive attackers (Phd)
- 12 December 2024 Lucas Bueri: Tba (Phd)
New publications
- Some Recent Publications
- Claire Maiza: Hardware and software analyses for precise and efficient timing analysis
- Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian, Ludovic Henrio, Gabriel Radanne: A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving
- Erwan Jahier, Karine Altisen, Stéphane Devismes: Exploring Worst Cases of Self-stabilizing Algorithms using Simulations
- Erwan Jahier, Karine Altisen, Stéphane Devismes, Gabriel B. Sant'Anna: Model Checking of Distributed Algorithms using Synchronous Programs
Jobs and internships
- Jobs and internships
- [Master] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
- PERSYVAL Master 2 Scholarships
- [Funded PhD] Annotations de sécurité pour compilateur optimisant formellement vérifié
- [Funded PhD] Quantitative analysis of software security against adaptive attacks
- [Master] Adapting Hardware Platforms to a Multi-Core Response Time Analysis Framework
- [Master] Analyzing fault parameters triggering timing anomalies
- [Master] Exploration by model-checking of timing anomaly cancellation in a processor
- [Master] Towards New Frontiers in Multi-Core Response Time Analysis?
- [Master]Leakage in presence of an active and adaptive adversary
- [PostDoc] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
