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VERIMAG

Susanne Graf

Susanne.Graf@imag.fr       
Tel: (+33) 4 57 42 22 19     
Office 283 in IMAG building
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Projects and Standardisation Activities
Past and Current

Networks of Excellence

The ARTIST Networks of Excellence aim at strengthening European research in Embedded Systems Design, promoting the emergence of this new multi-disciplinary area, and build a durable European research community on Embedded Systems Design.

ARTIST gathers key players in the following strategic domains: Modelling and Components, Hard Real-Time, Adaptive Real-Time, Compilers and Timing Analysis, Execution Platforms, Control for Embedded Systems, Testing and Verification.

  • IST Network of Excellence ARTIST DESIGN (2008-2012)
    • Cluster Real Time Components
  • IST Network of Excellence ARTIST2 Real-time embedded systems (2004-2008)
    • Coordination of the platform for Platform for Component Modelling and Verification
  • IST Initiative ARTIST Advanced Real-time Systems (2002-2004); look at the ARTIST Roadmap for embedded systems

Projects

European projects:

  • Integrated project SPEEDS Speculative and Exploratory Design in Systems Engineering (2006-2010):
    SPEEDS is a concerted effort to define the new generation of end-to-end methodologies, processes and supporting tools for safety-critical embedded system design. They will enable European systems industry to evolve from model-based design of hardware/software systems, towards integrated component based construction of complete virtual system models.
    The main expected results of the project are a modelling framework based on rich components including the relevant information for the verification of essential properties and for the generation of platform dependent code. A set of analysis tools will support the design process.
  • STREP COMBEST COMponent-Based Embedded Systems design Techniques (2008-2011):
    This project aimed at computational and analytical models for non-functional properties of embedded systems. The project pursued a dual approach, combining fundamental work with methods and tools for rigorous embedded systems design. The fundamental work in COMBEST proposed frameworks for the composition of heterogeneous components for achieving component-based design. A major challenge is inferring global properties of a system from the properties of its components.
  • IST Integrated project ASSERT Automated proof based System and Software Engineering for Real-Time (2004-2008).

    The main objective of ASSERT is to change the way system and software engineering is performed today to adopt a more reliable and scientific approach based on modelling, preservation of system properties and model transformation down to the final code.
    The results includes a process, a set of tool prototypes and case studies demonstrating the validity of the overall approach.
    This project was important for the dissemination of our results obtained in OMEGA. In particular, we adapted the OMEGA UML profile to describe a system at platform layer and used IFx for validation
  • Coordination of IST Project OMEGA Correct Development of Real-Time Embedded Systems in UML (2002-2005)

    The aim of the project was the definition of a development methodology in UML for embedded and real-time systems based on formal techniques. The concrete results are
    • A UML profile allowing to include timing information with operational design models and with operational or declarative requirement models. The real-time profile for UML 2, MARTE, has taken over some concepts of the OMEGA UML profile
    • A set of analyis and verification tools analysing models conformant to this profile.
  • IST Project INTERVAL (2000-2002)

    The aim of this project was to propose real-time extension for the ITU standards SDL, MSC and TTCN. Several of the extensions proposed are today part of the standards.
  • IST ADVANCE (2000 - 2003)
  • ESPRIT project VIRES (Verifying Industrial Reactive Systems, 1997-2000)

    one of the main aims of which was the Verification of a wireless ATM protocol. See also VIRES Workshop, June 2000 in Autrans
  • Eprit-BRA Project REACT (1993-1996)

    The aim of this project was foundational work on verification techniques. The result was an impressive list of publications, and a case study on the verification of a distriuted memory. VIRES was a follow-up project of REACT.
  • Eprit-BRA Project SPEC (1990-1993)

    The aim of this project was foundational work on verification techniques. The result was an impressive list of publications. REACT was the follow-up of this project.
  • Eprit R&D Project DELTA-4 (1988-1992)

    The aim ofthe project was to show the usefulness of formal design and requirement models. In particular, the ITU standard Estelle was used for modelling designs and temporal logic was used for the expression of requirements. Several instances of fault tolerant protocols realising an atomic multicast for different physical architectures have been used as case studies. We have provided the formal design and requirememnt models and verified them using the Xesar model-checker.

National projects:

  • CRTC, Certified and Configurable Real-Time Components, an exploratory project funded by the LabEx PERSYVAL-Lab (2015-2016)
  • French RNTL project OpenEmBEDD An open source platform making available model-based techniques for the development of real-time and embedded systems (2006-2009)

    OpenEmbeDD aims at developping an Eclipse-based "Model Driven Engineering" platform dedicated to Embedded and Real-Time systems. Its aim is to offer engineers who design and develop E/RT software the means to express, simulate, validate and test the targeted system before any component has solded on a circuit board.
    In this project, we disseminate the results of the Persiform and the SPEEDS project, in particular the tools developed in these projects.
  • French RNRT project PERSIFORM Performance engineering based on simulation of formal functional models (2005-2008)

    The project has defined a tool chain and a methodology allowing to use a functional service oriented model given by the designer (UML based) into a performance model analysed by a performance analysis tool used by the performance engineer (Hyperformix workbench). Allowing thus to ease the collaboration between the performance engineer and the designer.
  • ModoCop, Action de Recherche Coopérative on Model checking Of Concurrent Object-oriented Programs (2002-2003)
  • French RNRT Project PROUST (1999-2001)

    The aim of this project was to propose real-time extension for the ITU standard SDL. Its results have lead to the definition of th INTERVAL project with a broader scope

Industrial projects:

  • ESA Project Full-MDE (2010-1212)
    The aim of the ASSERT project - was dealing with non functional requirements, from system requirement capture to automatic code generation. However, some partners dedicated their work on functional requirements (without reaching the same level of maturity). The result of this work was the definition of an extension of the ASSERT project, supported by advanced technologies, such as UML Omega profile, AADL, gateway from ADDL to SCADE, ASN.1, SCADE and formal proof.
  • Bilateral Project with ESA (European Space Agency) Porting Omega to Rhapsody (2010-1211)
    This follow-up project of ASSERT has led to a significant improvement of the IF tool-box and its adaptation to the current version of the UML standard.
  • Cooperation Pragmadev (2006-2016)
    The PragmaDev company distributes some of validation components of the IF toolbox (static analysis, model-checking).
  • Bilateral Project with France Telecom R&D IF-2-TEST (2005-2007)
    The aim of this project was the use of IF to specify and generate test cases for vocal services that are executed autonomously and avoid human intervention.
  • Bilateral Project with CNET pro INTERVAL (2001-2002)
    The aim of this project was the application of the SDL timing extensions defined in INTERVAL and the IF toolbox to a case study, as well as the collaboration with CNET at ITU.
  • Bilateral Project with EADS ARIANE-5 (2000-2002)
    The aim of this project was an experiment of a global validation of a model of the Ariane-5 software described partly in SCADE and in SDL by using the VERIMAG tool boxes for IF and Lustre.

Standardisation Comittees

  • Associated rapporteur for the question on "time expressivenes and performance analysis in ITU-T related modelling languages", with particular interest in time extensions of ITU languages. (2000- 2002)