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Emplois et stages
Emplois et stages
Postdocs
[PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
Masters
[Master] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
Thèse
[Funded PhD] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
[Funded PhD] Improving Diagnosis for a Formal Verification Tool for Electrical Circuits at Transistor Level
Emplois et stages à Verimag
Nouvelles publications
Quelques Publications Récentes (Ressources Partagées)
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
On Self-stabilizing Leader Election in Directed Networks
Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian, Ludovic Henrio, Gabriel Radanne:
A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving
Erwan Jahier, Karine Altisen, Stéphane Devismes:
Exploring Worst Cases of Self-stabilizing Algorithms using Simulations
Karine Altisen, Pierre Corbineau, Stéphane Devismes:
Complexité certifiée d'algorithmes autostabilisants en rondes
David Monniaux, Sylvain Boulmé:
Chamois: agile development of CompCert extensions for optimization and security
Léo Gourdin, Benjamin Bonneau, Sylvain Boulmé, David Monniaux, Alexandre Bérard:
Formally Verifying Optimizations with Block Simulations
Karine Altisen, Stéphane Devismes, Anaïs Durand, Colette Johnen, Franck Petit:
Self-stabilizing Systems in Spite of High Dynamics
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
Pour battre à l'unisson, il faut que tous les chemins viennent de Rome
Offres d'emploi et stages
Offres d'emploi et stages (Ressources Partagées)
[Master] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
[PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
[Funded PhD] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
[Funded PhD] Improving Diagnosis for a Formal Verification Tool for Electrical Circuits at Transistor Level
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