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[PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
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[Master] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
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[Funded PhD] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
[Funded PhD] Improving Diagnosis for a Formal Verification Tool for Electrical Circuits at Transistor Level
Emplois et stages à Verimag
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Quelques Publications Récentes (Ressources Partagées)
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
Pour battre à l'unisson, il faut que tous les chemins viennent de Rome
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
Self-stabilizing Synchronous Unison in Directed Networks
Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian, Ludovic Henrio, Gabriel Radanne:
A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving
Léo Gourdin:
Lazy Code Transformations in a Formally Verified Compiler
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
Self-stabilizing synchronous unison in directed networks
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
On Self-stabilizing Leader Election in Directed Networks
Erwan Jahier, Karine Altisen, Stéphane Devismes, Gabriel B. Sant'Anna:
Model Checking of Distributed Algorithms using Synchronous Programs
Erwan Jahier, Karine Altisen, Stéphane Devismes:
Exploring Worst Cases of Self-stabilizing Algorithms using Simulations
Offres d'emploi et stages
Offres d'emploi et stages (Ressources Partagées)
[Master] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
[PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
[Funded PhD] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
[Funded PhD] Improving Diagnosis for a Formal Verification Tool for Electrical Circuits at Transistor Level
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