Accueil
>
Axes
>
Ressources partagées
>
Emplois et stages
>
Emplois et stages
Emplois et stages
Postdocs
[PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
Masters
[Master] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
Thèse
[Funded PhD] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
[Funded PhD] Improving Diagnosis for a Formal Verification Tool for Electrical Circuits at Transistor Level
Emplois et stages à Verimag
Nouvelles publications
Quelques Publications Récentes (Ressources Partagées)
Bruno Ferres, Oussama Oulkaid, Ludovic Henrio, Mehdi Khosravian, Matthieu Moy, Gabriel Radanne, Pascal Raymond:
Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
Self-stabilizing synchronous unison in directed networks
Karine Altisen, Stéphane Devismes, Anaïs Durand, Colette Johnen, Franck Petit:
Self-stabilizing Systems in Spite of High Dynamics
Erwan Jahier, Karine Altisen, Stéphane Devismes, Gabriel B. Sant'Anna:
Model Checking of Distributed Algorithms using Synchronous Programs
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
On Self-stabilizing Leader Election in Directed Networks
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
Self-stabilizing Synchronous Unison in Directed Networks
Erwan Jahier, Karine Altisen, Stéphane Devismes:
Exploring Worst Cases of Self-stabilizing Algorithms using Simulations
David Monniaux, Sylvain Boulmé:
Chamois: agile development of CompCert extensions for optimization and security
Offres d'emploi et stages
Offres d'emploi et stages (Ressources Partagées)
[Master] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
[PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
[Funded PhD] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
[Funded PhD] Improving Diagnosis for a Formal Verification Tool for Electrical Circuits at Transistor Level
Navigation
Rubriques
Verimag
Axes
Ressources partagées
Membres
Publications
Partenaires
Projets
Outils
Thèse en cours
Emplois et stages
ETiCS
Formal Proofs
PACS
MOHYTOS
FETLAS
Contact
Plan du site
Acces au Batiment
Contact
|
Plan du site
|
Site réalisé avec SPIP 4.2.13
+
AHUNTSIC
[CC License]
info visites
4003039
English
Français