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Emplois et stages
Postdocs
[PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
Masters
[Master] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
[Master] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
[Master] Analyzing fault parameters triggering timing anomalies
[Master] Exploration by model-checking of timing anomaly cancellation in a processor
Emplois et stages à Verimag
Nouvelles publications
Quelques Publications Récentes (Ressources Partagées)
Erwan Jahier, Karine Altisen, Stéphane Devismes, Gabriel B. Sant'Anna:
Model Checking of Distributed Algorithms using Synchronous Programs
Karine Altisen, Pierre Corbineau, Stéphane Devismes:
Complexité certifiée d'algorithmes autostabilisants en rondes
David Monniaux, Sylvain Boulmé:
Chamois: agile development of CompCert extensions for optimization and security
Erwan Jahier, Karine Altisen, Stéphane Devismes:
Exploring Worst Cases of Self-stabilizing Algorithms using Simulations
Léo Gourdin:
Lazy Code Transformations in a Formally Verified Compiler
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
Self-stabilizing Synchronous Unison in Directed Networks
Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian, Ludovic Henrio, Gabriel Radanne:
A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving
Karine Altisen, Stéphane Devismes, Anaïs Durand, Colette Johnen, Franck Petit:
Self-stabilizing Systems in Spite of High Dynamics
Offres d'emploi et stages
Offres d'emploi et stages (Ressources Partagées)
[Master] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
[PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
[Master] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
[Master] Analyzing fault parameters triggering timing anomalies
[Master] Exploration by model-checking of timing anomaly cancellation in a processor
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