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Emplois et stages
Postdocs
[PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
Masters
[Master] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
[Master] Adapting Hardware Platforms to a Multi-Core Response Time Analysis Framework
[Master] Towards New Frontiers in Multi-Core Response Time Analysis ?
[Master] Analyzing fault parameters triggering timing anomalies
[Master] Exploration by model-checking of timing anomaly cancellation in a processor
Emplois et stages à Verimag
Nouvelles publications
Quelques Publications Récentes (Ressources Partagées)
Léo Gourdin, Benjamin Bonneau, Sylvain Boulmé, David Monniaux, Alexandre Bérard:
Formally Verifying Optimizations with Block Simulations
Karine Altisen, Stéphane Devismes, Anaïs Durand, Colette Johnen, Franck Petit:
Self-stabilizing Systems in Spite of High Dynamics
David Monniaux, Sylvain Boulmé:
Chamois: agile development of CompCert extensions for optimization and security
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
On Self-stabilizing Leader Election in Directed Networks
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
Self-stabilizing synchronous unison in directed networks
Karine Altisen, Pierre Corbineau, Stéphane Devismes:
Complexité certifiée d'algorithmes autostabilisants en rondes
Bruno Ferres, Oussama Oulkaid, Ludovic Henrio, Mehdi Khosravian, Matthieu Moy, Gabriel Radanne, Pascal Raymond:
Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory
Erwan Jahier, Karine Altisen, Stéphane Devismes, Gabriel B. Sant'Anna:
Model Checking of Distributed Algorithms using Synchronous Programs
Offres d'emploi et stages
Offres d'emploi et stages (Ressources Partagées)
[Master] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
[PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
[Master] Adapting Hardware Platforms to a Multi-Core Response Time Analysis Framework
[Master] Towards New Frontiers in Multi-Core Response Time Analysis ?
[Master] Analyzing fault parameters triggering timing anomalies
[Master] Exploration by model-checking of timing anomaly cancellation in a processor
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