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Jobs and Internships
Postdocs
[PostDoc] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
Masters
[Master] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
PhD Thesis
[Funded PhD] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
[Funded PhD] Improving Diagnosis for a Formal Verification Tool for Electrical Circuits at Transistor Level
Jobs in the whole Verimag lab
New publications
Some Recent Publications (Ressources Partagées)
Léo Gourdin, Benjamin Bonneau, Sylvain Boulmé, David Monniaux, Alexandre Bérard:
Formally Verifying Optimizations with Block Simulations
Karine Altisen, Pierre Corbineau, Stéphane Devismes:
Complexité certifiée d'algorithmes autostabilisants en rondes
Erwan Jahier, Karine Altisen, Stéphane Devismes, Gabriel B. Sant'Anna:
Model Checking of Distributed Algorithms using Synchronous Programs
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
Self-stabilizing synchronous unison in directed networks
Bruno Ferres, Oussama Oulkaid, Ludovic Henrio, Mehdi Khosravian, Matthieu Moy, Gabriel Radanne, Pascal Raymond:
Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory
Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian, Ludovic Henrio, Gabriel Radanne:
A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
On Self-stabilizing Leader Election in Directed Networks
Erwan Jahier, Karine Altisen, Stéphane Devismes:
Exploring Worst Cases of Self-stabilizing Algorithms using Simulations
Jobs and internships
Jobs and internships (Ressources Partagées)
[Master] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
[PostDoc] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
[Funded PhD] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
[Funded PhD] Improving Diagnosis for a Formal Verification Tool for Electrical Circuits at Transistor Level
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