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[PostDoc] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
Masters
[Master] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
[Master] Adapting Hardware Platforms to a Multi-Core Response Time Analysis Framework
[Master] Towards New Frontiers in Multi-Core Response Time Analysis?
[Master] Analyzing fault parameters triggering timing anomalies
[Master] Exploration by model-checking of timing anomaly cancellation in a processor
Jobs in the whole Verimag lab
New publications
Some Recent Publications (Ressources Partagées)
Karine Altisen, Pierre Corbineau, Stéphane Devismes:
Complexité certifiée d'algorithmes autostabilisants en rondes
David Monniaux, Sylvain Boulmé:
Chamois: agile development of CompCert extensions for optimization and security
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
Pour battre à l'unisson, il faut que tous les chemins viennent de Rome
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
Self-stabilizing Synchronous Unison in Directed Networks
Léo Gourdin:
Lazy Code Transformations in a Formally Verified Compiler
Erwan Jahier, Karine Altisen, Stéphane Devismes, Gabriel B. Sant'Anna:
Model Checking of Distributed Algorithms using Synchronous Programs
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
Self-stabilizing synchronous unison in directed networks
Léo Gourdin, Benjamin Bonneau, Sylvain Boulmé, David Monniaux, Alexandre Bérard:
Formally Verifying Optimizations with Block Simulations
Jobs and internships
Jobs and internships (Ressources Partagées)
[Master] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
[PostDoc] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
[Master] Adapting Hardware Platforms to a Multi-Core Response Time Analysis Framework
[Master] Towards New Frontiers in Multi-Core Response Time Analysis?
[Master] Analyzing fault parameters triggering timing anomalies
[Master] Exploration by model-checking of timing anomaly cancellation in a processor
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