SYRF Project

LIST OF DELIVERABLES


Warning: All 1999 deliverables are under construction.
A draft of the Final Report is also under construction

TASK 1997 1998 1999
0.1 Management deliv. 0.1.1 deliv. 0.1.2 deliv. 0.1.3
0.2 Dissemination deliv. 0.2.1 deliv. 0.2.2 deliv. 0.2.3
1 Case studies     deliv. 1
2 Combination of formalisms deliv. 2.1 deliv. 2.2 deliv. 2.3
3.1 Symbolic abstraction of automata deliv. 3.1.1 deliv. 3.1.2 deliv. 3.1.3
3.2 Use of Stalmarck method deliv. 3.2.1 deliv. 3.2.2 deliv. 3.2.3
3.3 Handling numerical properties deliv. 3.3.1 deliv. 3.3.2 deliv. 3.3.3
3.4 Use of theorem provers deliv. 3.4.1 deliv. 3.4.2 deliv. 3.4.3
3.5 Automatic testing deliv. 3.5.1 deliv. 3.5.2 deliv. 3.5.3
4/5.1 Fundamentals deliv. 4/5.1.1 deliv. 4/5.1.2 deliv. 4/5.1.3
4/5.2 Code distribution   deliv. 4/5.2.2 deliv. 4/5.1.3
4/5.3 Timing analysis deliv. 4/5.3.1 deliv. 4/5.3.2 deliv. 4/5.3.3
4/5.4 Verification of mixed A/S systems deliv. 4/5.4.1 deliv. 4/5.4.2  
6.1 VHDL/Verilog deliv. 6.1.1 deliv. 6.1.2 deliv. 6.1.3
6.2 Mixed controller/datapath design deliv. 6.2.1 deliv. 6.2.2 deliv. 6.2.3
7 Analog/discrete synchronous design deliv. 7.1 deliv. 7.2 deliv. 7.3