SYRF Project

Approach:

Thanks to results obtained in previous periods (6.1.2, 6.2.2), two domains have been explored this year. The first one is High Level Pre-Synthesis and the second one is Functional Uunits Assignment under Constraints During Data Path Generation. Our activity in the latter is prolongation of these taken in the first one.

In the context of the first activity we have proposed a new methodology based on Signal internal representation which is HCDG Hierarchical Conditional Dependency Graph for improving synthesis process. Combination of pre-synthesis and powerful HCDG representation is a principal novelty of our approach. HCDG offers the following advantages:

• unification of control and data representation (leading to insensitivity to syntactic variance), extensive and uniform identification of mutual exclusiveness,
• possibility to eliminate a higher number of false paths,
• formally proved graph optimizing transformations thanks to the formal semantics of the HCDG,
• more efficient scheduling of conditional behaviors by either ameliorating the performance of standard algorithms or proposing a new algorithm tailored to the HCDG generation of efficient HDL code to exploit the underlying tool capabilities while circumventing their limitations.

Our high level pre-synthesis process is composed of several steps. Firstly, pre-scheduling transformations are performed on HCDG. One advantage of these transformations is that description becomes insensitive to syntactic variances. Next, scheduling under constraints is applied followed by post-scheduling transformations, which are necessary to incorporate in the HCDG information about resource sharing and speculative execution. The last step is a VHDL code generation at the behavioral level using extended lower level optimizations like: don?t care values assignment and value range information incorporation.

The result of high level pre-synthesis process is a VHDL code written at behavioral level. One of the possible extensions is generating a code directly at RTL level due to an information provided by scheduler. We have investigated this possibility. In this context we have explored functional units assignment in order to assure the same activity level of all functional units in data path. This is necessary to avoid thermal shock in integrated circuits. We have developed a new methodology based on static measure of operators activities. This information is necessary to build a fitness function used by genetic algorithm, which find the best operators binding to functional units. We have also investigated register-sharing methodology that we have extended by using exclusiveness information.

Achieved Results:

• A quasi-automatic pre-prototype has been developed implementing high level pre-synthesis step.
• A pre-prototype has been developed for finding the best possible operators binding to functional units.
• A pre-prototype has been developed for efficiency register sharing.

J.C.Le Lann, C. Wolinski, Load balancing and Functional Unit Assignment in High-Level Synthesis, SCI'99/ISAS'99 Florida July 31 - August 4, 1999 (postscript)

A. Kountouris, C. Wolinski, High Level Pre-Synthesis Optimization Steps using Hierarchical Conditional Dependency Graphs, EUROMICRO'99, IEEE Computer Society Press, Milano, Itali, AUG 1999. (postscript)

A. Kountouris, C. Wolinski, Combining Speculative Execution and ConditionalResource Sharing toEfficiently Schedule Conditional Behaviors,Proceedings of ASP-DAC'99,IEEE Computer Society Press, Hong-Kong, Jan. 18-21, 1999. (postscript)

A.Kountouris Outils pour la validation Temporelle et l?Optimisation de Programmes Synchrones, Univ. Rennes 1 thèse 1998. (Postscript)