SYRF Project

Task 6.1: "VHDL/Verilog"

Abstract of deliverable 6.1.2

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Achieved Results:

There are natural formal connections between synchronous reactive formalisms and models of synchronous hardware circuits (RTL netlists). These similarities have been recently exploited, both to apply optimisation techniques designed for circuits to synchronous processes, and conversely to give constructive causal meaning to circuits.

We have defined and implemented a first prototype version of a translator from DC to the Verilog hardware description language at the RTL level (structural Verilog). The difficulty here is mainly that the resulting code should be semantically equivalent to the original synchronous DC code, and be fit to enter most hardware synthesis tools.