SYRF Project

Tasks 4/5.1 and 4/5.2: "Integrating synchrony & asynchrony:
fundamentals and distributed codee generation"

Abstract of deliverables 4/5.1.3 and 4/5.2.3

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Foreword

For the final report, we have found relevant and interesting to discuss the approach developed in the framework of the SYRF project, together with the approach developed by G. Berry and E. Sentovich (in the framework of the CMA-Inria lab. at Sophia Antipolis, and Berkeley Cadence lab.).

The approach developed at Inria in the framework of SYRF mainly had distributed software architectures in its target. In contrast, the approach by Berry & Sentovich has been motivated by studies in synchronous/asynchronous hardware circuits.

1. The SYRF approach

Problem setting

There are several issues that need to be considered in fundamental studies related to synchrony & asynchrony, namely:
  1. How to distribute correctly a synchronous program on a given, possibly asynchronous, architecture? What are the available theoretical results? What are the assumptions required, for the supporting execution architecture?
  2. In what extend a property proved for the original synchronous program is still valid for the same one, running on a distributed, possibly asynchronous, architecture?
  3. What support can be provided (with theoretical justifications) for the reuse of pre-existing components? How can encapsulation be guaranteed correct?
This is the type of question which we want to provide theoretical support for. The difficulties we are faced with are the following:

Achieved Results

(a magenta color indicates a new result, not available at the previous review)

Perspectives

It turns out that our work on desynchronisation is also relevant to object oriented software development for reactive systems. In the framework of a joint Alcatel contract with C. Jard, B. Caillaud, and J-M. Jézéquel, we have focussed on UML method and notations and we have started developing a semantic backbone for them, called  BDL  (Behavioural Description Language). BDL is a formalism which has both a synchronous and an asynchronous semantics, and allows to handle partial (nondeterministic) designs. From the mathematical viewpoint, BDL is a multiclock synchronous language handling transition systems over directed graphs. Concrete syntax is a variation of the Statecharts. The requirements for our theory of desynchronisation to apply are acceptable for UML: objects can communicate synchronously or asynchronously. Thanks to isochrony and its compositional nature, we can envision using synchronous techniques for developing object classes, and have possibly asynchronous, dynamic, instanciation and deployment.

Documents

We have prepared a short deliverable (8 pages) summarizing the whole results of the project for this task, and drawing perspectives.
 

Publications

  1. [BCLg99a]A. Benveniste, B. Caillaud and P. Le Guernic. ``Compositionality in dataflow synchronous languages: specification & distributed code generation.'' Information and Computation, to appear.(new)
  2. [BCLg99b]A. Benveniste, B. Caillaud and P. Le Guernic. ``From synchrony to asynchrony.'' In J.C.M. Baeten and S. Mauw, editors, CONCUR'99, Concurrency Theory, 10th International Conference, vol. 1664 of Lecture Notes in Computer Science,  162-177. Springer V.,  1999.
  3. [Sacres98]A. Benveniste. ``Safety critical embedded systems: the SACRES approach.'' In Formal techniques in Real-Time and Fault Tolerant Systems, FTRTFT'98 school, Lyngby, Denmark, Sept 1998.
  4.  [BC99]  A. Benveniste, P. Caspi. ``Distributing synchronous programs on communication media of time triggered type.'' Draft note, 1999.
  5. [TBCLg99]  J-P. Talpin, A. Benveniste, B. Caillaud, P. Le Guernic. ``HIerarchic normal forms for desynchronization.'' Draft paper, 1999.
  6. [Btransp99]  A. Benveniste. `Distributing synchronous programs.'' Slides, FM'99, Toulouse.

2. The Berry & Sentovich approach (a sketch of...)

This approach addresses directly the GALS (Globally Asynchronous, Locally Synchronous) hardware architecture, with the so-called CFSM network model (Codesign Finite State Machine), see [BS99]. CFSM networks are networks of synchronous circuits: each node 1/ reads inputs, 2/ computes, and 3/ writes outputs instantaneously. The communication network is asynchronous, and obey the following model: Therefore CFSM nodes can have partial input assignments, in which only part of the input status buffers store a 1. When its input assignment is total (all status buffers sre set to 1), then the considered node can proceed and performs its synchronous transition.

As the write/read operations in the communication channels are asynchronous, this calls for a confluent technique for performing assignments, in which, for a total assignment (all status buffers sre set to 1), the values stored in the input value buffers are identical irrespective of the particular ordering of the writings in the {status,value}-buffers.

A previous result from Berry on the constructive semantics of Esterel had established the equivalence of the following two properties for (possibly cyclic) digital circuits:

  1. For any given latch- and input-pattern, the circuit stabilizes to the same set of values for the variables and registers, irrespective of the needed delay for each gate of wire to stabilize.
  2. The corresponding netlist of boolean equations has a well-defined and unique solution according to the so-called constructive logic. According to this logic, netlists of boolean equations are solved by iteratively  propagating facts, i.e., properties in the three-valued logic {?,0,1} where ? denotes the undefined status. The solution is well-defined when this iteration has a unique fixpoint, in which all variables are set to either 0 or 1 (but not ?).
>From noticing the point 1, it was tempting to rely on execution scheme 2 (the so-valled constructive semantics) to implement CFSM communication, as it satisfies the needed confluence requirements. This technique has been implemented in the framework of the POLIS project, and is reported in  [BS99] .
 

Publications

  1. [BS99] G. Berry and E. Sentovich. ``An implementation of constructive synchronous programs in POLIS''. To appear in "Design Automation for Embedded Systems"

3. Discussion and comparison

There are similarities and differences, we discuss them. Then we investigate how far these approaches could complement.

Similarities

Differences

Complementary?

The conditions for applicability of the two methods look very similar. There is no reason why one could not combine the approaches. In particular, constructive semantic techniques and related execution schemes could be used for a more powerful handling of the finite state control part of STS following the SYRF approach.