The proposal

The focus of research on design of large hardware circuits and Systems-on-Chips has shifted from Register-Transfer Level (RTL) to Electronic System Level (ESL). ESL in fact consists of a multiplicity of sublevels, depending more and less on extra-functional features such as approximate timing. The most famous modeling formalism for ESL design is named SystemC (see the official OSCI site).

Defining clear levels for component descriptions allow to devise a platform-based approach, where individual (IP) components and subsystems, possibly imported, may be assembled into larger systems. There exist a number of such platforms (with sometimes wide differences). In France one can mention two academic join efforts, ANR SoClib and UNISIM. The open-source initiative GreenSoCs is also worth noticing here. On the other hand there is a profusion of (more or less complete) commercial solutions: CoWare, Synopsys Innovator/Designware , VaST Virtutech Simics, Mentor Graphics Visual Elite, Carbon Design Systems and certainly a few others.

In general these platforms remain at the level of mere simulation and component-based assembly of large systems from IP cores. They do not truly consider issues of non-functional features apart from (approximate physical) timing, nor the combination of distinct levels of modeling (to this end SystemC introduced the notion of transactor, as to relate a single atomic behavior at abstract level to a more complex concrete representation, which coined the term Transaction-Level Modeling (TLM)). Efficient simulation and also co-simulation at multiple levels is still an advanced research topic.

There have been attempts to translate ESL TLM programs into formal Models of Computation and Communication (MoCCs), either synchronous or asynchronous. Conversely one can also contemplate producing SystemC from dedicated formalisms or expressing MoCCS directly in the language. This approach allows to use formal models with semantics to conduct analysis and/or transformations. Here one can cite Lussy / Pinapa ([MMM-emsoft05, MMM-jDAES05] from one of our partner), Scoot [BKS-tacas08], SystemCXML [BPMS-05] and HetSC [HV-07], as academic tools, Esterel Studio, Synfora Pico Express amongst others.

Multi-clock Synchronous languages provide an alternative to SystemC simulation semantics, by introducing logical virtual clocks. Synthetizability conditions are computed as correct causality by so-called clock-calculus. While C/C++-based modeling allows easy co-simulation of RTOS and commodity applications with abstract hardware, synchronous languages draw a close connection to real-time critical embedded software of reactive nature. In this range one can mention Esterel Studio as a commercial tool, and academic efforts such as Academic Esterel, PolyChrony, Lucid Synchrone, Lustre, the Kiel Esterel Processor.

The topic of efficient execution of ESL programs has been tackled both for SystemC [GPMT04,BPG04] and for Synchronous formalisms, and in comparison. Much remains to be done in this respect (hence part of this proposal), specially when non-functional aspects are relevant.

The modeling of energetic (low-power) and thermal aspects for efficient simulation of systems is a hot current topic, tackled in academic effort projects such as ANR Open-People and Athole (in which some of the current project members are participants). For commercial tools, our member Docea Power is offering a dedicated solution called Docea Power ACEplorer. Other commercial platforms dedicated to energy (but often not thermal) solutions are Synopsys Eclypse, and a range of EDA vendors (UPF solutions providers).

Representation standards are key to allow a design flow methodology where IP models are exchanged and shared. This is true of any modeling level. Apart from OSCI SystemC being an IEEE standard, relevant normalization efforts comprise SPIRIT IP-XACT for interfaces and platform integration, OMG UML MARTE for general-purpose modeling of both Embedded Real-Time Architecture and Application, and Allocation mechanisms. UPF and CPF are two formats for energy representation proposed by EDA vendor consortia.

Low-Power modeling has been the special focus theme of the last edition of the CIM PACA SAME forum which gathers locally the regional organizations active in the microelectronics area.

The fundamental objective is the understanding of high-level models for energy-consumption in embedded systems: what are they, how can they be used, and what kind of guarantee can they provide on the final systems? We will identify the information that are needed/available at high levels of description. We will take into account the possible uses of the high-level models (mainly virtual prototyping and simulation). We expect to reconcile: Various types of formal models that have been developed for concurrent and timed systems, and their few extensions to non-functional properties; The necessary extension of these models to include energy consumption, especially in systems where energy and functionality are closely linked The need for realistic design flows: first, in a high-level model used for virtual prototyping, we should not need the precise information that will be available much later when the final chip is built; second, if there are several models of the same system, at several levels of abstraction, then there should be a way to go from one to the other in a controlled way (the energy models should not need to be written from scratch).

These objectives are original and, if reached, will provide a significant advance with respect to the state of the art. The academic state of the art is made of: a relatively well-understood set of formal models for synchronous, asynchronous, Globally-Asynchronous-Locally-Synchronous (GALS) systems, etc.; plus a large set of proposals of languages for the description of heterogeneous systems, not always comparable, and seldom usable for industrial-size systems. The industrial state of the art is a large set of methods and tools that have evolved from low-level design methods and tools, with a clear objective of usability (one of the reasons why SystemC has become a standard is that it is based on the C family of languages, which make it possible to build a co-simulation engine for heterogeneous components) ; the essential points of high-level functional and non-functional modeling are not always well understood; or, even when they are well understood, the methods always reflect a compromise between efficient simulation, and correct abstractions. There is a clear need for collaborative research, where academic partners can bring their expertise in formal models and reasoning, while the industrial partners bring their precise knowledge of the properties that really matter in high-level models, and the realistic constraints on the use of languages and models in real design flows.

The difficult points are the following: how to identify the information on energy consumption, component per component, and organize them into a high-level model of energy consumption for the whole system? How to relate the various abstraction levels?

Energy-consumption models for low-power are clearly related to efficiency and timing models through the effects of now-spreading techniques such as frequency/voltage scaling, clock- and power-gating, to name only the best established ones. With the help of so-called power-managers, links are made between energy consumption and timing performances of non-functional nature (i.e., functionality-preserving). Clock- and power-gating should find their abstract counter-parts in virtual logical clocks modeling; frequency scaling would loosely correspond to regular periodic sub-clocking of original full-speed master clocks. Such intuitively valid assumptions still have to be straightened into a well-defined, sound formal approach.

Our intentions concerning innovative design flows are best described going backwards: accurate energy-consumption and thermal analyses, using the type of modeling currently proposed by Docea Power, require candidate critical runs to provide their meaningful power consumption and temperature worst cases. How does one get these plausible critical runs? They may currently be obtained from a larger consumption/thermal model, disregarding functionality, or from a functional/timed model, disregarding consumption. A joint formal modeling would aim at abstracting and combining both functional/timing aspects and energy/power ones, with the proper level of abstraction and the proper abstracted values of parameters. As in most compositional approaches in this domain, the precise characterization of individual elements which shall then be combined is of utter importance, and the difficulty in obtaining good data in that respect should never be downplayed. Once a potential covering critical run has been identified at a more abstract level in a large system, one may play it back in simulation to build its concrete monolithic part and compute its non-functional features, or apply it component-wise to obtain local such results, which may be assembled then for an approximate result. These may be considered in terms of the computation complexity of models. They illustrate issues in interplays between compositional modeling and abstraction levels. Based on the models obtained as the results of fundamental research, the objectives are to improve existing methods and tools for the virtual prototyping of low-power systems. This includes simulation methods, component-based methods, etc. The technical result, at the end of the project, will be the integration of the fundamental results in the design flows of the industrial partners. The DOCEA method will benefit from the formalization of the models, especially the model of the power-manager. The design flow based on TLM and SystemC will benefit: 1) from the fundamental works on the levels of abstraction; 2) from the comparison between SystemC-like simulation engines and synchronous multi-clock execution principles.

At the end of the project, the following elements will help evaluate the results: Do the formal models developed in the project answer the questions that arise in industrial frameworks? Are they rich enough to include the information that really matter? Has the design flow improved on the treatment of the practical case study being handled ? Clarifying and formalizing the high level models can help designing them, and transforming them. Are the models usable for new tasks? Non formalized models can be used for simulation only; formalized ones allow the use of formal verification methods, like runtime verification. Are the high-level models more faithful? This is an intrinsic question when designing high-level models. The industrial partners will provide their usual evaluation methods for this point.

Task 1: Identification of a generic Case-study & synthesis

The objective of task 1 is to ensure that the project is conducted starting from relevant information, including a clear identification of the industrial context and needs, and caring for capitalization of expertise and reusability of know-how. At the end of the project, all the partners will produce a synthesis document.

Task 2: High-Level Functional/energy modeling

This task is devoted to the study of formal models for high-level modeling of functional and non-functional aspects of SoCs. The three academic partners are the main participants. The two industrial partners contribute their expertise in modeling and model engineering.

The coupling of the functional and the non-functional parts is essential for getting relevant results when the embedded software is executed on the virtual platform. So far, virtual platforms integrate models of IP with functional aspects only. An effort is required to determine how mixed functional and non-functional component models can be composed and exploited under simulation environments.

Task 3: Simulation at several levels of abstraction

This task is devoted to the mechanization of the formal models studied in task 2, and to the proposal of solutions for their integration into current tools. The three academic partners are the main participants. The two industrial partners contribute their expertise in modeling and model engineering. They will implement some of the solutions in Task 4. The idea is not to develop simulation tools from scratch. The existing solutions should be reused and adapted as much as possible. This may require that the formal models defined in Task 2 be encoded. The first point is: how to express and simulate the formal energy models using the languages and the event-driven simulators that are the standard of the domain (e.g., SystemC)? A second point concerns the integration of functional and non-functional aspects. In the formal models of task 2, we hope to integrate the functionality, the timing, and the energy, in such a way that the semantics of the model covers these three points. Existing solutions and tools often rely on co-simulation between a functional model, and some energy model that might be available separately. Bridging the gap between integrated formal models, and co-simulations of two separated models, is an important point. Finally, some of the results of Task 2, namely those on multi-clock synchronous languages, can be implemented using existing tools of the synchronous family (Esterel, Lustre, ReactiveML). We will study new execution mechanisms based on these tools, and able to express the semantics of our integrated models.

task 4: Industrial use and Developments on case-studies

This task is devoted to the actual use of the solutions studied in tasks 2 and 3, in industrial tools and methods. The two industrial partners are the main participants. The three academic participants participate in Task 4 to help adapting the results of Tasks 2 and 3. Task 2 will provide an integrated formalization of all the aspects needed in a high-level model; Task 3 will show how to express and simulate those formal models using existing tools; Task 4 first gathers all these results, to develop a complete solution for the generic case-study of Task 1. Then, the industrial partners investigate the modifications of their methods and tools, based on this first experiment.