Home
>
Archives
>
Synchrone (Archive)
>
Some Synchrone Former Members
>
Some Synchrone Former Members
Some Synchrone Former Members
Tayeb Bouhadiba
Laure Danthony-Gonnord
David Stauch
Youssef Bouzouzou
Claude Helmstetter
Ludovic Samper
Olivier Bezet
Yanhong Liu
Jérôme Cornet
Jan Mikac
Lionel Morel
Fabien Gaucher
Yann Rémond
Muriel Jourdan
News
NEWS
Joseph Sifakis
Understanding and Changing the World, From Information to Knowledge and Intelligence
Conferences
Workshop CAPITAL 2022: sCalable And PrecIse Timing AnaLysis for multicore platforms
July 31, 2022
ASL 2022 : Advances in Separation Logic
Seminars
Seminars
31 May 2022
Matheus Schuh:
Safe implementation of hard real-time applications on many-core platforms (Phd)
3 June 2022
Capital Workshop :
Workshop capital 2022 : scalable and precise timing analysis for multicore (...)
14 June 2022
Joel Goossens:
Real-time computing, foundation
16 June 2022
Joel Goossens:
Periodicity of real-time priority driven schedulers with preemption delay on (...)
21 June 2022
Joel Goossens:
Real-time computing, multiprocessor scheduling problems
New publications
Some Recent Publications
Karine Altisen, Stéphane Devismes, Anaïs Durand, Colette Johnen, Franck Petit:
On Implementing Stabilizing Leader Election with Weak Assumptions on Network Dynamics
Stéphane Devismes, Pascal Lafourcade:
Un jour sans fin
Léo Gourdin:
PhD Student session: formally verified postpass scheduling with peephole optimization for AArch64
Karine Altisen, Pierre Corbineau, Stéphane Devismes:
Exact Worst Case Self-Stabilization Time
Jobs and internships
Jobs and internships
(un)decidability of polyhedral invariant inference
Thèse CIFRE : Cybersecurity - Fault injection attacks
Thèse/PhD Position - Coverage Measures for Machine Learning Enabled Cyber-Physical Systems
verified decomposition of arithmetic operators
Verified global value numbering
[L3/M1/M2 Internship] Topics in Formally Verified Compilation
[master or PhD] Convex polyhedra in floating point
[master] automatic insertion of countermeasures in a verified compiler
[Master] Decision Procedures for Separation Logic Modulo Theories of Data
[Master] Design and Evaluation of Strategies for Automated Proofs using Reasoning Modulo Equivalence
[master] formally verified hash-consing
[Master] Local Reasoning about Reconfigurable Component-based Systems
[Master] Multi-core Interference analysis and Global Scheduling
[Master] Simulation of Distributed Algorithms
[Master] Verifying Concurrent Systems with Automata over Infinite Alphabets
Browsing
Sections
Verimag
Topics
Contact
Site Map
Building Access
Contact
|
Site Map
|
Site powered by SPIP 3.2.15
+
AHUNTSIC
[CC License]
info visites
1851606
English
Français