Verimag

VERIMAG + STMicroelectronics common projects [2002...[

The Synchrone Group at VERIMAG and STMicroelectronics have been working together on TLM related problems since 2002. See the poster attached, which describes the tools that were developed, and how they connect together. The main problems we are looking at are the following:

  • How to connect SystemC to formal verification tools; this relies on a front-end for SystemC called PINAPA, and on a semantic extractor able to transform abstract syntax trees of SystemC models into some format suitable for model-checking or abstract interpretation tools. See work by M. Moy.
  • How to cover correctly the potential parallelism that is present in a SystemC design, and that is supposed to represent faithfully the physical parallelism of the hardware? Our tool relies on dynamic partial order reduction techniques. See work by C. Helmstetter.
  • How to define precisely the nature of the information that should be present in pure functional models (also called TLM-PV, for "programmer’s view") and in timed models (also called TLM-PVT, for "programmer’s view + time)? How to construct a PVT model from a PV one without modifying its functionality, as seen by the developer of the embedded software? See work by J. Cornet.
  • How to define precisely what a TLM component should be, be it written in SystemC or nor? See work by G. Funchal.
  • How to design a parallel version of the SystemC engine, in order to exploit multi-core architectures and improve simulation speed? See work by Y. Bouzouzou.
  • How to model energy consumption at the TLM level? This is the subject of the HELP project.

Projects:


Attached documents

Poster TLM

17 July 2009
Document : PDF
1.5 Mb

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