Verimag

Jérôme Cornet

supervisor: F. Maraninchi - PhD 2004-2008

Separation of Functional and Non-Functional Aspects in Transactional Level Models of Systems-on-Chip

Committee (April 25, 2008):

  • Frédéric Pétrot (President, Pr. Grenoble INP)
  • Robert de Simone (Reviewer, DR INRIA Sophia Antipolis)
  • Reinhard von Hanxleden (Reviewer, PR, U.Kiel, Germany)
  • Florence Maraninchi (Supervisor, Pr. Grenoble INP, VERIMAG Lab.)
  • Laurent Maillet-Contoz (Advisor, Project Manager, STMicroelectronics)
  • Ian O’Connor (Examinator, Pr. EC Lyon)

The slides of the defense are available here.

Public LinkedIn Profile.

Publications

2016

  1. Parallel Simulation of Loosely Timed SystemC/TLM Programs: Challenges Raised by an Industrial Case Study. Denis Becker, Matthieu Moy, Jérôme Cornet - MDPI Electronics - [bibtex]
  2. SycView: Visualize and Profile SystemC Simulations. Denis Becker, Matthieu Moy, Jérôme Cornet - Workshop on Design Automation for Understanding Hardware Designs (DUHDe) - [bibtex]

2015

  1. Challenges for the Parallelization of Loosely Timed SystemC Programs. Denis Becker, Matthieu Moy, Jérôme Cornet - IEEE International Symposium on Rapid System Prototyping (RSP) - [bibtex]

2013

  1. Fast and Accurate TLM Simulations using Temporal Decoupling for FIFO-based Communications. Claude Helmstetter, Jérôme Cornet, Bruno Galilée, Matthieu Moy, Pascal VIVET - Design, Automation and Test in Europe (DATE) - [bibtex]
  2. Co-Simulation of Functional SystemC TLM Models with Power/Thermal Solvers. Tayeb Bouhadiba, Matthieu Moy, Florence Maraninchi, Jérôme Cornet, Laurent Maillet-Contoz, Ilija Materic - Virtual Prototyping of Parallel and Embedded Systems (VIPES) - [bibtex]

2012

  1. Co-Simulation of a SystemC TLM Virtual Platform with a Power Simulator at the Architectural Level: Case of a Set-Top Box. Jérôme Cornet, Laurent Maillet-Contoz, Ilija Materic, Sylvian Kaiser, Hela Boussetta, Tayeb Bouhadiba, Matthieu Moy, Florence Maraninchi - Design Automation Conference - [bibtex]

2008

  1. A Method for the Efficient Development of Timed and Untimed Transaction-Level Models of Systems-on-Chip. Jérôme Cornet, Florence Maraninchi, Laurent Maillet-Contoz - Design Automation and Test in Europe (DATE) - [bibtex]
  2. SystemC/TLM Semantics for Heterogeneous System-on-Chip Validation. Florence Maraninchi, Matthieu Moy, Jérôme Cornet, Laurent Maillet-Contoz, Claude Helmstetter, Claus Traulsen - 2008 Joint IEEE-NEWCAS and TAISA Conference - [bibtex]
  3. Separation of Functional and Non-Functional Aspects in Transactional Level Models of Systems-on-Chip. Jérôme Cornet - [bibtex]

2007

  1. A SystemC/TLM semantics in Promela and its possible applications. Claus Traulsen, Jérôme Cornet, Matthieu Moy, Florence Maraninchi - 14th Workshop on Model Checking Software SPIN - [bibtex]

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