Verimag

HELP

ANR Arpège, 2009-2013

 Presentation:

The HELP project focuses on functional and non-functional high-level models for the design of low-power embedded systems. The need for low-power systems is now well admitted, in the domain of embedded systems in general. This is particularly true for sensor networks or consumer electronics (mobile phones and all kinds of portable devices), because of lifetime constraints. But this is also true for other (non autonomous) embedded systems, in a world concerned with sustainable development.

The other important point for HELP concerns high-level models. Our motivations and our work program are based on the following premises: embedded systems are more and more complex, and time-to-market demands impose very strong constraints on the development methods. One of the key points explaining the increase in complexity is the wide spreading of multiprocessor hardware platforms; another one is the growing importance of software in electronic devices. To meet all these constraints, the design of an embedded system can start from a virtual prototype (i.e., an executable high level model, which can be available early in the design cycle for early decisions). In the specific domain of System-on-Chip (SoC) design, transaction-level modeling (TLM) has started to make its way into industrial-strength development methods. The idea is to build an executable model of the hardware execution platform, so that software developers can start developing their code on it, long before the actual chip is available. While TLM models do respect the global abstract functionality, sublevels have been defined to take into account extra-functional aspects. Simpler models are easier to develop and simulate, but less accurate for analysis (for instance timing may go from untimed/causal to approximate-timed to cycle-accurate). The virtual prototype platform has to be relevant for software validation, i.e., be functionally faithful. But its faithfulness with respect to non-functional features of the final chip is also an important question. Low-Power energy saving is now such a key non-functional aspect.

The separation between functional and non-functional aspects can be rather tricky at times. In real-time systems or synchronous circuits, precise timing may be an integral part of the functionality. In other cases they provide performance complexity aspects that are relevant for analysis but do not impact the functionality. The same goes with power modeling, for instance with the introduction of Power Managers in the system description. Still, energy models usually depart sensibly from functional models. The challenge of the HeLP proposal is to study means to provide a component-based, virtual prototype platform approach which relates and combines the various modeling levels mentioned above, with their inherent abstraction levels and the efficient simulation techniques that are associated with each. A key point is the ability to model the intrinsic coupling between functionality and energy (a power manager takes decisions depending on functional information). We plan to do so by capitalizing on expertise by Docea Power and LEAT on Energy/Power modeling, by ST on varying TLM levels with different timing accuracy, by Verimag and INRIA-Aoste on high-level modeling and semantic issues (underlying efficient simulation), and by LEAT on scheduling. As a matter of fact previous collaborations have raised the level of awareness of all partners on all issues, with a central concern for practical model-based design-flow and virtual prototype platforms. The practical relevance of the approach, and its validation against previous, lower-level results shall be asserted through a common case study provided by industrial partners.

 Partners:

 Verimag people involved:

  • Florence Maraninchi
  • Matthieu Moy
  • Karine Altisen
See online : The project website

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