Accueil
>
Archives
>
RSD (Archive)
>
Obsolete
>
Rigorous Design of Component-Based Systems — The BIP (...)
>
BIP Tools
Download Form
Please fill the following form
Name
Affiliation
e-mail
Navigation
Rubriques
Verimag
Axes
Contact
Plan du site
Acces au Batiment
Actualités
ACTUALITÉS
Joseph Sifakis
Understanding and Changing the World, From Information to Knowledge and Intelligence
Conférences
Workshop CAPITAL 2022 : sCalable And PrecIse Timing AnaLysis for multicore platforms
July 31, 2022
ASL 2022 : Advances in Separation Logic
Séminaires
Séminaires
31 mai 2022
Matheus Schuh:
Safe implementation of hard real-time applications on many-core platforms (Phd)
3 juin 2022
Capital Workshop :
Workshop capital 2022 : scalable and precise timing analysis for multicore (...)
14 juin 2022
Joel Goossens:
Real-time computing, foundation
16 juin 2022
Joel Goossens:
Periodicity of real-time priority driven schedulers with preemption delay on (...)
21 juin 2022
Joel Goossens:
Real-time computing, multiprocessor scheduling problems
Nouvelles publications
Quelques Publications Récentes
Léo Gourdin, Sylvain Boulmé:
Certifying assembly optimizations in Coq by symbolic execution with hash-consing
Guillaume Brau, Mohammed Foughali:
Contract-Based Verification of Model Transformations: A Formally Founded Approach
Karine Altisen, Stéphane Devismes, Anaïs Durand, Colette Johnen, Franck Petit:
On Implementing Stabilizing Leader Election with Weak Assumptions on Network Dynamics
Abdelhakim Baouya, Salim CHEHIDA, Samir Ouchani, Saddek Bensalem, Marius Bozga:
Generation and verification of learned stochastic automata using k-NN and statistical model checking
Offres d'emploi et stages
Offres d'emploi et stages
(un)decidability of polyhedral invariant inference
Thèse CIFRE : Cybersecurity - Fault injection attacks
Thèse/PhD Position - Coverage Measures for Machine Learning Enabled Cyber-Physical Systems
verified decomposition of arithmetic operators
Verified global value numbering
[L3/M1/M2 Internship] Topics in Formally Verified Compilation
[master or PhD] Convex polyhedra in floating point
[master] automatic insertion of countermeasures in a verified compiler
[Master] Decision Procedures for Separation Logic Modulo Theories of Data
[Master] Design and Evaluation of Strategies for Automated Proofs using Reasoning Modulo Equivalence
[master] formally verified hash-consing
[Master] Local Reasoning about Reconfigurable Component-based Systems
[Master] Multi-core Interference analysis and Global Scheduling
[Master] Simulation of Distributed Algorithms
[Master] Verifying Concurrent Systems with Automata over Infinite Alphabets
Contact
|
Plan du site
|
Site réalisé avec SPIP 3.2.15
+
AHUNTSIC
[CC License]
info visites
1851213
English
Français