Home
>
Verimag
>
Seminars
Seminar details
salle A. Turing CE4
18 February 2014 - 14h00
Safety Problems are NP-complete for Flat Integer Programs with Octagonal Loops
by
Radu Iosif
from VERIMAG
Abstract: a tutorial on rigorous acceleration techniques
Browsing
Sections
Verimag
Direction and Boards
Members
Publications
Tools
Ongoing Phd Thesis
Jobs and Internships
Projects
Partners
Workshops and Conferences
Seminars
Archives
Documents
Topics
Contact
Site Map
Building Access
News
Seminars
Seminars
19 January 2026
Alban Reynaud:
Formal verification of borrow-checking by local commutation diagrams
New publications
Some Recent Publications
Bruno Ferres, Oussama Oulkaid, Matthieu Moy, Gabriel Radanne, Ludovic Henrio, Pascal Raymond, Mehdi Khosravian:
A Survey on Transistor-Level Electrical Rule Checking of Integrated Circuits
Iulia Dragomir, Carlos Redondo, Tiago Jorge, Laura Gouveia, Iulian Ober, Marius Bozga, Maxime Perrotin:
Specification and model-checking of space systems in the TASTE toolset
Marius Bozga, Radu Iosif, Arnaud Sangnier, Neven Villani:
Counting Abstraction and Decidability for the Verification of Structured Parameterized Networks
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
Self-stabilizing synchronous unison in directed networks
Jobs and internships
Jobs and internships
[Funded PhD] Fault Injection Attacks: Automated Analysis of Counter-Measures At The Binary Level
[Master] Decision Procedure for Equivalence Relations
[PostDoc] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
Contact
|
Site Map
|
Site powered by SPIP 4.4.5
+
AHUNTSIC
[CC License]
info visites
5261274
English
Français