Verimag

Time-Critical Applications on Multicore Platforms

A diagram of the tool chain for code generation is shown in the figure above. The top-part represents a high-level design, serving as input to the tool chain. Currently we support high level designs from the DOL Critical framework. The framework should provide the model of the application (task graph) and the model of deployment (mapping). The application model includes both the task communication structure (here: the DOL-Cr XML) and the task functions (here: the C files). The mapping file contains the mapping and scheduling tables, currently we support the TTS (time triggered with synchronization) tables, in the XML format of DOL Critical. The frontend is a tool that translates the high-level models into BIP model. The BIP models define the executable semantics for all elements in the system, including the tasks and the schedulers. The bottom part of the figure represents the compilation from BIP to an executable code of the multicore platform that runs on top of a multi-thread BIP runtime library. We assume a shared memory multicore platform with POSIX threads.

Taste2BIP: Extension of DOLC2BIP to Taste

Taste2BIP flow extends the DOLC2BIP flow by graphical input in TASTE, which is an open-source software engineering environment for embedded real-time applications provided by European Space Agency. TASTE is distributed pre-installed on a Linux virtual machine, which is required to be downloaded first: https://taste.tuxfamily.org/ and then you can install the given flow on the virtual machine following the installation instructions. TASTE gives powerful means for graphical input using functions communicating via interfaces. Similar to DOLC2BIP, this flow also targets its operation onto embedded multi-core platforms with POSIX threads. The application is designed using a Fixed Priority Process Network (FPPN) and is automatically deployed on the embedded multi-core platform. FPPN is a Model of Computation for multi-core programming where real-time periodic/sporadic tasks (processes) communicate via channels. For deployment our tools first translate the TASTE design into DOLC and then (a newer version) of DOLC2BIP translates the DOLC design into BIP. Using real-time BIP real-time environment (RTE), the design can be simulated or deployed on multi-core platform. We used a satellite Guidance, Navigation and Control (GNC) application as a use case. To get started:

  1. Download and install Linux Virtual Machine with Taste
  2. In the virtual machine download the file taste2bip.tgz
  3. Unpack tastebip.tgz and follow documentation instructions

These tools were originally developed in the context of CERTAINTY European project and MoSaTT-CMP project


Tool Chain Download Links:


Older Version of the Tool Chain (v3.2, 23 September 2014):


Tool Documentation References

[RefSched] P. Poplavko, R. Kahil, D. Socci, S. Bensalem, M. Bozga. Technical Note. Ensuring Schedulability for Embedded Multi-cores.

[RefUseCase] F. Gioulekas, P. Poplavko, A. Zerzelidis, P. Katsaros, P. Palomo. Technical Note. Application Use Case for Multi-core Schedulability.

[DOLC2BIP-Manual] P. Poplavko, P. Bourgos, M. Bozga, S. Bensalem. (DOLC-to-BIP Manual): Multi-Core Code Generation for Timing-critical Applications using BIP Tools.

[DOLC-BIP-Theory] G. Giannopoulou, P. Poplavko, et al, DOL-BIP-Critical: A Tool Chain for Rigorous Design and Implementation of Mixed-Criticality Multi-Core Systems. TIK Report No. 363, ETH, Zurich, 2016.


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