Home
>
Archives
>
Synchrone (Archive)
>
Some Synchrone Former Members
>
Some Synchrone Former Members
Some Synchrone Former Members
Jan Mikac
Lionel Morel
Fabien Gaucher
Yann Rémond
Muriel Jourdan
Tayeb Bouhadiba
Laure Danthony-Gonnord
David Stauch
Youssef Bouzouzou
Claude Helmstetter
Ludovic Samper
Olivier Bezet
Yanhong Liu
Jérôme Cornet
News
NEWS
Joseph Sifakis elected member of the National Academy of Sciences
Junior professorship chair on verifiable / explainable artificial intelligence
Seminars
Seminars
16 May 2024
Gaiyun Liu:
Modeling, analysis, and supervisory control of networked discrete event systems
30 May 2024
Mohamed Maghenem:
A hybrid-systems framework for distributed gradient-based estimation
New publications
Some Recent Publications
Marius Bozga, Radu Iosif, Joseph Sifakis:
Verification of component-based systems with recursive architectures
Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian, Ludovic Henrio, Gabriel Radanne:
A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving
Bruno Ferres, Oussama Oulkaid, Ludovic Henrio, Mehdi Khosravian, Matthieu Moy, Gabriel Radanne, Pascal Raymond:
Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
On Self-stabilizing Leader Election in Directed Networks
Jobs and internships
Jobs and internships
[Master] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
PERSYVAL Master 2 Scholarships
Junior professorship chair on verifiable / explainable artificial intelligence
[Funded PhD/PostDoc] Countermeasures to (transient) Side-Channel Attacks in a Formally Verified Compiler
[Funded PhD] Annotations de sécurité pour compilateur optimisant formellement vérifié
[Funded PhD] Quantitative analysis of software security against adaptive attacks
[Master] Analyzing fault parameters triggering timing anomalies
[Master] Exploration by model-checking of timing anomaly cancellation in a processor
[Master] Formal Methods for the Verification of Self-Adapting Distributed Systems
[Master] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
[Master]Leakage in presence of an active and adaptive adversary
[PostDoc] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
Browsing
Sections
Verimag
Topics
Contact
Site Map
Building Access
Contact
|
Site Map
|
Site powered by SPIP 4.2.8
+
AHUNTSIC
[CC License]
info visites
3962460
English
Français