Accueil
>
Archives
>
Synchrone (Archive)
>
Thèmes de recherche Synchrone
>
Virtual Prototyping and Simulation
xxx
Navigation
Rubriques
Verimag
Axes
Contact
Plan du site
Acces au Batiment
Actualités
Nouvelles publications
Quelques Publications Récentes
Léo Gourdin:
Lazy Code Transformations in a Formally Verified Compiler
Karine Altisen, Pierre Corbineau, Stéphane Devismes:
Certification of an exact worst-case self-stabilization time
Florence Maraninchi:
Revisiting "Good" Software Design Principles To Shape Undone Computer Science Topics
Sylvain Boulmé:
Construire des logiciels fiables
Offres d'emploi et stages
Offres d'emploi et stages
[Master] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
[Funded PhD] Annotations de sécurité pour compilateur optimisant formellement vérifié
[Funded PhD] Quantitative analysis of software security against adaptive attacks
[Master] Adapting Hardware Platforms to a Multi-Core Response Time Analysis Framework
[Master] Analyzing fault parameters triggering timing anomalies
[Master] Exploration by model-checking of timing anomaly cancellation in a processor
[Master] Towards New Frontiers in Multi-Core Response Time Analysis ?
[Master]Leakage in presence of an active and adaptive adversary
[PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
Contact
|
Plan du site
|
Site réalisé avec SPIP 4.2.16
+
AHUNTSIC
[CC License]
info visites
4225771
English
Français