Related Lab Topic :
PhD
Weicheng He
is preparing a PhD thesis in Verimag
from May 2023
to April 2026,
under the supervision of
Saddek Bensalem
Related Lab Topic :Fetlas
Related Lab Topic :
Browsing
News
Seminars
New publications
- Some Recent Publications
- Mnacho Echenim, Radu Iosif, Nicolas Peltier: Entailment is Undecidable for Symbolic Heap Separation Logic Formul\ae with Non-Established Inductive Rules
- Paolo Torrini, Sylvain Boulmé: A CompCert Backend with Symbolic Encryption
- Bruno Ferres, Oussama Oulkaid, Ludovic Henrio, Mehdi Khosravian, Matthieu Moy, Gabriel Radanne, Pascal Raymond: Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory
- Léo Gourdin, Benjamin Bonneau, Sylvain Boulmé, David Monniaux, Alexandre Bérard: Formally Verifying Optimizations with Block Simulations
Jobs and internships
- Jobs and internships
- [Master] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
- PERSYVAL Master 2 Scholarships
- [Master] Modeling and Characterizing Fault Attacks exploiting the Memory Architecture
- [Master] Proved-Secure Compilation for RISC-V Processor
- [Master] A Solver for Monadic Second Order Logic of Graphs of Bounded Tree-width
- [Master] Analyzing fault parameters triggering timing anomalies
- [Master] Exploration by model-checking of timing anomaly cancellation in a processor
- [Master] Formal Methods for the Verification of Self-Adapting Distributed Systems
- [Master] Modeling and Simulation of Modular Robots with DR-BIP
- [Master] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
- [Master]Leakage in presence of an active and adaptive adversary
- [PhD] Logical Foundations of Self-Adapting Distributed Systems
- [PostDoc] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences