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Ongoing Phd Thesis
PhD
Lucas Bueri is preparing a PhD thesis in Verimag from September 2021 to August 2024, under the supervision of
Radu Iosif
Radu Iosif
Related Lab Topic :
Mohytos
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NEWS
Junior professorship chair on verifiable / explainable artificial intelligence
Poste de professeur des universités (section 27)
Seminars
Seminars
4 April 2024
Sébastien Michelland:
Abstract interpreters: a monadic approach to modular verification
11 April 2024
Andrei Paskevich:
Coma: an intermediate verification language with explicit abstraction barriers
2 May 2024
Matthieu Moy:
How to build a broken system?
New publications
Some Recent Publications
Karine Altisen, Pierre Corbineau, Stéphane Devismes:
Certified Round Complexity of Self-Stabilizing Algorithms
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
Pour battre à l'unisson, il faut que tous les chemins viennent de Rome
David Monniaux, Léo Gourdin, Sylvain Boulmé, Olivier Lebeltel:
Testing a Formally Verified Compiler
Karine Altisen, Pierre Corbineau, Stéphane Devismes:
Certification of an exact worst-case self-stabilization time
Jobs and internships
Jobs and internships
[Master] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
PERSYVAL Master 2 Scholarships
Junior professorship chair on verifiable / explainable artificial intelligence
Poste de professeur des universités (section 27)
[Funded PhD/PostDoc] Countermeasures to (transient) Side-Channel Attacks in a Formally Verified Compiler
[Funded PhD] Annotations de sécurité pour compilateur optimisant formellement vérifié
[Funded PhD] Quantitative analysis of software security against adaptive attacks
[Master] A Solver for Monadic Second Order Logic of Graphs of Bounded Tree-width
[Master] Analyzing fault parameters triggering timing anomalies
[Master] Exploration by model-checking of timing anomaly cancellation in a processor
[Master] Formal Methods for the Verification of Self-Adapting Distributed Systems
[Master] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
[Master]Leakage in presence of an active and adaptive adversary
[PostDoc] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
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