@incollection{Moy05b,
title = { Chapter 5.9, Formal Verification },
author = {Moy, Matthieu},
year = {2005},
booktitle = {Transaction-Level Modeling with {SystemC}. {TLM} Concepts and Applications for Embedded Systems},
pages = {190--206},
publisher = {Springer},
team = {SYNC},
}
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- Some Recent Publications
- Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes: Self-stabilizing Synchronous Unison in Directed Networks
- Karine Altisen, Pierre Corbineau, Stéphane Devismes: Complexité certifiée d'algorithmes autostabilisants en rondes
- Marius Bozga, Radu Iosif, Joseph Sifakis: Verification of component-based systems with recursive architectures
- Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian, Ludovic Henrio, Gabriel Radanne: A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving
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- [Master] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
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- Junior professorship chair on verifiable / explainable artificial intelligence
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- [Funded PhD/PostDoc] Countermeasures to (transient) Side-Channel Attacks in a Formally Verified Compiler
- [Funded PhD] Annotations de sécurité pour compilateur optimisant formellement vérifié
- [Funded PhD] Quantitative analysis of software security against adaptive attacks
- [Master] Analyzing fault parameters triggering timing anomalies
- [Master] Exploration by model-checking of timing anomaly cancellation in a processor
- [Master] Formal Methods for the Verification of Self-Adapting Distributed Systems
- [Master] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
- [Master]Leakage in presence of an active and adaptive adversary
- [PostDoc] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences