@phdthesis{Rom7,
title = { High-level component-based models for functional verification of systems-on-a-chip },
author = {Romenska, Yuliia},
year = {2017},
school = {Grenoble Alpes University, France},
team = {SYNC},
}
bibtex
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- 24-28 Novembre 2025 Synchron 2025
Séminaires
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- 13 novembre 2025 Yann Herklotz: Towards scalable verification and efficient hardware generation using verified (…)
- 21 novembre 2025 Oussama Oulkaid: Formal models of integrated circuits for transistor level electrical verification (Phd)
- 25 novembre 2025 Véronique Cortier: Electronic voting: design, attack, and formal verification
- 1er décembre 2025 Sylvain Boulme: Introduction à la programmation orientée objet en crystal
- 4 décembre 2025 Jannik Laval: A venir (thème cybersécu)
- 11 décembre 2025 Thaïs Baudon: A venir (thème: compilation optimisant les représentations mémoire)
Nouvelles publications
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Récentes
- Marius Bozga, Radu Iosif, Florian Zuleger: Regular Grammars for Sets of Graphs of Tree-Width 2
- Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes: On Self-stabilizing Leader Election in Directed Networks
- Bruno Ferres, Oussama Oulkaid, Matthieu Moy, Gabriel Radanne, Ludovic Henrio, Pascal Raymond, Mehdi Khosravian: A Survey on Transistor-Level Electrical Rule Checking of Integrated Circuits
- Akram Idani, Yves Ledru, German Vega: Formal model-driven security combining B-method and process algebra: The B4MSecure platform
Offres d'emploi et stages
- Offres d'emploi et stages
- [Funded PhD] Fault Injection Attacks : Automated Analysis of Counter-Measures At The Binary Level
- [Master] Decision Procedure for Equivalence Relations
- [Master]Leakage in presence of an active and adaptive adversary
- [PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences