P. Bourgos, A. Basu, S. Bensalem, K. Huang, J. Sifakis
Integrating Architectural Constraints in Application Software by Source-to-Source Transformation in BIP (2011)
Integrating Architectural Constraints in Application Software by Source-to-Source Transformation in BIP (2011)
TR-2011-1.pdf
Keywords: System Level Design, Hardware Architecture, Mapping, Hardware Constraints, Performance Estimation
Abstract: Performance of embedded applications strongly depends on features of the hardware platform on which they are deployed. A grand challenge in complex embedded systems design is developing methods and tools for modeling and analyzing the behavior of an application software running on a given hardware architecture. We propose a rigorous method that allows to obtain a model which faithfully represents the behavior of a mixed hardware/software system from a model of its application software and a model of its underlying hardware architecture. The method takes a model of the application software in BIP, a model of the hardware architecture in XML and a mapping associating read and write operations of the application software with execution paths in the architecture. It builds a model of the corresponding mixed hardware/software system in BIP. The latter can be simulated and analyzed for verification of both functional and extra-functional properties. The method consists in progressively enriching the application software model. It involves three steps: 1) The generation of a BIP model of the application software; 2) The generation of a BIP model of the hardware architecture; 3) The composition of the two models. The steps are implemented by application of source-to-source transformations that are correct-by-construction. In particular they preserve functional properties of the application software. The obtained system model is highly parametrized and allows flexible integration of specific target architecture features, such as bus policy and scheduling policy of the processors. The method has been implemented for application software and hardware architectures described in the DOL tool for performance evaluation. It is illustrated through the construction of a system model of an MJPEG application running on an MPARM architecture.
