Room 206 (2nd floor, badged access)
6 February 2023 - 14h00
Using Model Checking for Electrical Rule Checking of Integrated Circuits at Transistor Level
by Bruno FERRES from LIP (equipe CASH)
Abstract: This seminar introduces my research thematics, which focus on high level
methodologies for design and verification of electronic circuits.
After a small summary of my past activities, first as an engineering
student and then as a PhD student, this talk with present my current
work at LIP (Lyon).
This work is done within a collaboration with Verimag (with Pascal
Raymond and Oussama Oulkaid) and Aniah (a Grenoble-based company), where
we investigate the problem of Electrical Rule Checking (ERC) of
integrated circuits at transistor level.
Aniah already provides a solution which can identify some electrical
errors at billion-transistor level very quickly, through an innovative
approach to the problem.
In the context of this collaboration, we consider using formal methods,
such as model-checking, to improve this solution.
Notably, we provide several semantics of circuits which can be used for
reasoning and proofs, as well as a software prototype which can be used
for circuit analysis.