Auditorium (Building IMAG)
3 June 2022 - 09h00
Workshop CAPITAL 2022 : sCalable And PrecIse Timing AnaLysis for multicore platforms
by CAPITAL Workshop from sCalable And PrecIse Timing AnaLysis for multicore
Abstract: Free attendance but mandatory registration by May 1st, 2022.
Friday, June 3th, 2022. Grenoble and possible remote attendance
with a keynote of Renato Mancuso, Boston University From Memory Partitioning to Management through Fine-grained Profiling and Control
and 5 invited speakers:
** Hai Nam Tran** (Lab-STICC - Université de Bretagne Occidentale, Brest, France)
** Ignacio Sanudo Olmedo** (Università degli studi di Modena e Reggio Emilia, Modena, Italy)
** Julien Forget ** (CRIStAL, Université de Lille, France)
** Daniel Casini ** (ReTiS Lab, Scuola Superiore Sant'Anna, Pisa, Italy)
** Patricia Balbastre ** (Universitat Politècnica de València, Valencia, Spain)
More details and registration:
https://www-verimag.imag.fr/Workshop-CAPITAL-2022-sCalable-And.html
Topic of the seminar:
The design and the implementation of time-critical applications upon multi-core processors are considered. Multi-core processors have the potential to offer high computing power. Unfortunately, their extensive use of shared resources (e.g.,caches, DRAM, buses, etc.) makes the design and the implementation difficult to predict: especially in situations where hard real-time constraints must be satisfied. Recent works show that an important challenge is to design a precise and scalable timing analysis. To address this challenge the research community consider closely both sides of the system: software and hardware. The aim of this co-design approach is therefore to guarantee scalability, precision and low complexity of the solution without compromising flexible efficient use of resources. The solution must be tailored for the target application and platform. In particular by identifying the shared resources (memory, bus, cache) and by reducing the complexity based on interference delay using, for instance, a tailored mapping/scheduling, bandwidth regulator. The solution must be also based on a good use of the hardware architecture (memory banks, cache, communication media) with techniques like physical/temporal partitioning to obtain a precise solution.
Organisers
Joël Goossens (ULB, Brussels, Belgium)
Claire Maiza (Grenoble INP/Ensimag, Verimag, Grenoble, France)
Juan M Rivas (Universidad de Cantabria, Santander, Spain)
Thomas Carle (Toulouse University, IRIT, Toulouse, France)
