Auditorium du Bât IMAG
16 June 2016 - 14h00
Power reduction in sequential circuits (Phd Defense)
by Jan Lanik from VERIMAG
16 June 2016 - 14h00
Power reduction in sequential circuits (Phd Defense)
by Jan Lanik from VERIMAG
Abstract: The topic of this thesis are methods for power reduction in digital circuits by reducing average switching on the transistor level. These methods are structural in the sense that they are not related to tuning physical properties of the circuitry but to the internal structure of the implemented logic and therefore independent on the particular technology. We developed two novel methods. One is based on optimizing the structure of the combinatorial part of a circuit during synthesis. The second method is focused on sequential part of the circuit. It looks for clock gating conditions that can be used to disable idle parts of a circuit and uses formal methods to prove that the function of the circuit will not be altered.
Jury:
- Prof. Ahmed Bouajjani, IRIF, Universite Paris Diderot (president)
- Prof. Sharad Malik, Princeton (rapporteur)
- Prof. Roderick Bloem, Graz (rapporteur)
- Dr. Dejan Nickovic, Austrian Institute of Technology (examinateur)
- Dr. Julien Legriel, Synopsys (examinateur)
- Dr. Oded Maler, VERIMAG (co-directeur de these)
- Dr. Fahim Rahim, Synopsys (co-directeur de these)
