An article on Verimag in Minalogic News

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• Verimag
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• Building Access

News

Seminars

• Seminars
  • 27 March 2025 Youssouf Oualhadj: Robust timed synthesis

New publications

• Some Recent Publications
  • Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian, Ludovic Henrio, Gabriel Radanne: A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving
  • David Monniaux, Sylvain Boulmé: Chamois: agile development of CompCert extensions for optimization and security
  • Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes: On Self-stabilizing Leader Election in Directed Networks
  • Basile Pesin, Sylvain Boulmé, David Monniaux, Marie-Laure Potet: Formally Verified Hardening of C Programs against Hardware Fault Injection

Jobs and internships

• Jobs and internships
  • [Professor] Université Grenoble Alpes
  • [Funded PhD] Annotations de sécurité pour compilateur optimisant formellement vérifié
  • [Funded PhD] Fault Injection Attacks: Automated Analysis of Counter-Measures At The Binary Level
  • [Funded PhD] Quantitative analysis of software security against adaptive attacks
  • [Master] Analyzing fault parameters triggering timing anomalies
  • [Master]Leakage in presence of an active and adaptive adversary
  • [PostDoc] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences