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Multi-core Interference analysis and Global Scheduling
Advisers: Claire Maiza and Lionel Rieg Context: In hard real-time systems, the implementation must ensure guaranteed bounds on execution time and delays. On multi-core platforms, any shared resources access may cause interferences (shared memory and shared bus). The interference analysis must ensure bounded delay for shared resource accesses. The estimation of such delays for timing analysis or taking them into account for the implementation is a hot topic. Possible Subjects: - interference analysis for timing analysis (hardware and software models) - proof of non-interfering applications or guaranteed estimated bounds (timing anomaly) - implementation of critical applications on multi-core - scheduling implementation on the Kalray MPPA Coolidge
Advisers: David Monniaux, Claire Maïza In order to prove bounds on the execution time of programs, it is useful to know if memory accesses are in-cache or out of cache. One can do this by static analysis. Obviously, static analysis cannot always conclude (whether an access is in cache may depend on the execution path etc.) but one wants to reduce the cases where one cannot conclude. For caches with LRU (least recently used) replacement policies, good analysis methods are known. The goal of the internship (which may lead into a PhD) is to look at other policies.
Any older topic below may be discussed also.
Advanced cache analyzes
Advisers: David Monniaux, Claire Maïza In order to bound the worst-case execution time (WCET) of programs, or to detect possible side-channel information leaks (security issue), it is necessary to statically analyze their behavior on the memory cache hierarchy. The topic of the internship is the design and implementation of improved cache analyzes.
Exploration of timing anomaly impact on processor execution for critical real-time systems
Advisers: Lionel Rieg, Claire Maiza