BIP -- Incremental Component-based Construction of Real-time Systems

Tasks runing on dedicated CPU's

This is a performance evaluation problem with timed tasks processing events from a bursty event generator. (Source http://www.tik.ee.ethz.ch/~leiden05)
The model is a serial connection of a bursty event generator with three tasks T1, T2 and T3, running on independent CPU's. A task can execute as soon as its predecessor has finished. A task on completion triggers an event for its successor. If the successor is busy, the event is queued. The block diagram for the model is shown below:

The atomic components for this model are 'Task' and the 'EventGenerator'. A generic timed model of 'Task' which can be used either as a simple task or as a preemptable task is shown below.

It has a timed variable 'delay' to enforce best case execution time (BCET) and worst case execution time (WCET).

The 'EventGenerator' component has a period T, jitter J, J>T, and has a minimum inter-arrival time D between successive events generated. Its model is as shown below.

The compound component 'System' is a serial connection of the EventGenerator and the three instances of Task, T1, T2 and T3 , as shoen in the architecture below. In this model, the tasks are non-preemptable, so the ports 'preempt' and 'resume' are not assiciated to connectors.

Running an execution gives the end-to-end delay of each event processed by the System, with details of the execution (CPU) time and waiting time. Here time means the number of 'tick' transitions occurred.