Verimag

Multicore Code Generation for Time-critical Applications

A diagram of the tool chain for code generation is shown in the figure above. The top-part represents a high-level design, serving as input to the tool chain. Currently we support high level designs from the DOL Critical framework. The framework should provide the model of the application (task graph) and the model of deployment (mapping). The application model includes both the task communication structure (here: the DOL-Cr XML) and the task functions (here: the C files). The mapping file contains the mapping and scheduling tables, currently we support the TTS (time triggered with synchronization) tables, in the XML format of DOL Critical. The frontend is a tool that translates the high-level models into BIP model. The BIP models define the executable semantics for all elements in the system, including the tasks and the schedulers. The bottom part of the figure represents the compilation from BIP to an executable code of the multicore platform that runs on top of a multi-thread BIP runtime library. We assume a shared memory multicore platform with POSIX threads.

Tool Chain Documentation:

PDF - 150.5 kb

Tool Chain Download :

TGZ - 11.8 Mb

Latest Version : v3.2, 23 September 2014

These tools were originally developed in the context of CERTAINTY European project.


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