STMicroelectronics

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• Acces au Batiment

Nouvelles publications

• Quelques Publications Récentes (Ressources Partagées)
  • Léo Gourdin, Benjamin Bonneau, Sylvain Boulmé, David Monniaux, Alexandre Bérard: Formally Verifying Optimizations with Block Simulations
  • Léo Gourdin: Lazy Code Transformations in a Formally Verified Compiler
  • Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes: Self-stabilizing synchronous unison in directed networks
  • Karine Altisen, Pierre Corbineau, Stéphane Devismes: Complexité certifiée d'algorithmes autostabilisants en rondes
  • Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian, Ludovic Henrio, Gabriel Radanne: A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving
  • Erwan Jahier, Karine Altisen, Stéphane Devismes: Exploring Worst Cases of Self-stabilizing Algorithms using Simulations
  • Karine Altisen, Stéphane Devismes, Anaïs Durand, Colette Johnen, Franck Petit: Self-stabilizing Systems in Spite of High Dynamics
  • Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes: On Self-stabilizing Leader Election in Directed Networks

Offres d'emploi et stages

• Offres d'emploi et stages (Ressources Partagées)
  • [Master] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
  • [PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
  • [Master] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
  • [Master] Analyzing fault parameters triggering timing anomalies
  • [Master] Exploration by model-checking of timing anomaly cancellation in a processor