Verimag

BIP System Designer

The BIP System Designer is the complete tool-set to obtain a system model of a mixed software/hardware system, that can be simulated, analyzed (verification of functional + extra-functional properties), and used to generate the software stack (application software + hardware dependent software) for a target platform.

The tools are classified as follows:

 Frontend

  • Translation of application software model into application model in BIP. The translator from DOL to BIP is here.

The complete list of translators is here.

  • Transformation of BIP application model by weaving the model of underlying hardware architecture and mapping, to obtain the mixed software/hardware system model in BIP. The descriptions of the hardware architecture and mapping are defined using a XML-like syntax. The tool is under development. The method is available in the technical report TR-2011-1.

 Profiler

  • Method for performance analysis based on the system model. The tool is under development. Some concrete results are available within the technical report TR-2011-1.

 Backend

  • Backend code generation tools allowing to generate the low-level C code corresponding to the application mapped on the platform. The code generation step solves issues related to the allocation and initialization of the communication channels, implementation of communication primitives using the low-level primitives available on the platform, allocation and scheduling of processes (whenever several are mapped onto the same core) etc...

This feature is currently being developed for MPARM platform.

 Examples

MJPEG Decoder

Cholesky Factorization


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