Open Positions
Please find a long version on Verimag webpage and/or contact me for more details.
Postdoc
Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
The implementation of critical applications on multi/many-core platforms is a hot topic in real-time research community. The interferences on shared resources such as shared memory, impacts the execution of critical tasks and their timing analysis. We focus on applications modeled by a direct acyclic graph (DAG) of tasks where edges represent precedence constraints and communications. Our previous work revisits the link between timing analysis and implementation with a collaboration of code orchestration, mapping/scheduling, interference analysis and schedulability. We consider the DAG as a periodic application with one global period. However, applications described by DAGs are generally multi-peridic or subject to execution modes. The idea is to analyze and integrate the execution mode to our implementation/analyses.
The candidate must have knowledge on real-time systems, timing analysis or Synchronous DAG applications. This postdoc is funded by the ANR project CAOTIC
Collaborators: Claire Maiza and Pascal Raymond
Master
Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
Advisers: Claire Maiza and Pascal Raymond
The implementation of critical applications on multi/many-core platforms is a hot topic in real-time research community. The interferences on shared resources such as shared memory, impacts the execution of critical tasks and their timing analysis. We focus on applications modeled by a direct acyclic graph (DAG) of tasks where edges represent precedence constraints and communications. Our previous work revisits the link between timing analysis and implementation with a collaboration of code orchestration, mapping/scheduling, interference analysis and schedulability. We consider the DAG as a periodic application with one global period. However, applications described by DAGs are generally multi-peridic or subject to execution modes. The idea is to analyze and integrate the execution mode to our implementation/analyses. One of these steps will be explored during the Internship.
The candidate must have knowledge on real-time systems, timing analysis or Synchronous DAG applications.
Towards New Frontiers in Multi-Core Response Time Analysis?
Advisers: Bruno Ferres and Claire Maiza
Providing strong guarantees on the temporal bevahior of critical-systems is crucial in sever-ous domains, such as avionics, aeronautics, automotive or nuclear. In order to do so, techniques have been developed to provide Worst-Case Execution Times (or WCET) of programs used in those critical systems, making it possible to bound the response time of the software on some processors – namely, on mono-core processors.
However, with the raising of multi- and many-core systems, it becomes more difficult to bound the response time of a given program, as it may interfere with other tasks at runtime. Analysis of the Worst Case Response Time (or WCRT) must hence consider not only the WCET of the task, but also the timing penalties that may occur due to the interferences of the other tasks (e.g., cache and bus accesses, that may introduce unplanned delays). Last but not least, the analysis must also consider the hardware systems on which the software is being executed, as several aspects of the hardware can impact both the WCET and the interferences.
In this context, the Multicore Interference Analysis framework (or MIA) has been proposed in Verimag [1, 2]. This framework can be used to compute the WCRT of a given program, for a given hardware platform. It is based on a dual approach: WCET are computed with hypotheses on the interferences, then interference delays are computed and added to the response time. However, such approach relies on several abstractions, which might lead to over-pessimistic estimations of the global WCRT of the task.
In the context of the ANR project CAOTIC (Collaborative Actions on Timing Interferences, a research project funded by the Agence Nationale de la Recherche, led by Verimag), we want to investigate how the dual-approach WCRT analysis could be improved. In particular, we think that the frontier between the WCET and the interference estimations could be refined, making it possible to tighten the bounds on the WCRT.
The goal of this internship is hence to study how the WCRT analysis could be improved. In particular, we are interested in knowing if the over-approximations could be tackled in the WCET computation, in the interferences computation, or during the combination of both aspects.
The following contributions are hence expected:
• identify several execution scenarios where WCET and interferences are overlapping;
• for each scenario:
1. characterize the conditions leading to such overlapping;
2. identify which analysis is responsible for the additional penalty in the WCRT;
3. modify the analysis framework to tighten the WCRT.
Contributions are hence expected both on the theoretical aspects of the framework, and on the practical side, ideally leading to the improvement of the computed WCRT.
[1] M. Schuh, Implantation sûre d’applications temps-réel critiques sur plateforme pluri-coeur. PhD thesis, Université Grenoble Alpes, 2022. Available at [https://theses.hal.science/tel-03827333](https://theses.hal.science/tel-03827333).
[2] H. Rihani, Analyse temporelle des systèmes temps-réels sur architectures pluri-coeurs. PhD thesis, Université Grenoble Alpes, 2017. Available at [https://theses.hal.science/tel-01875711](https://theses.hal.science/tel-01875711).
Adapting Hardware Platforms to a Multi-Core Response Time Analysis Framework
Advisers: Bruno Ferres and Claire Maiza
Providing strong guarantees on the temporal bevahior of critical-systems is crucial in sever-ous domains, such as avionics, aeronautics, automotive or nuclear. In order to do so, techniques have been developed to provide Worst-Case Execution Times (or WCET) of programs used in those critical systems, making it possible to bound the response time of the software on some processors – namely, on mono-core processors.
However, with the raising of multi- and many-core systems, it becomes more difficult to bound the response time of a given program, as it may interfere with other tasks at runtime. Analysis of the Worst Case Response Time (or WCRT) must hence consider not only the WCET of the task, but also the timing penalties that may occur due to the interferences of the other tasks (e.g., cache and bus accesses, that may introduce unplanned delays). Last but not least, the analysis must also consider the hardware systems on which the software is being executed, as several aspects of the hardware can impact both the WCET and the interferences.
In this context, the Multicore Interference Analysis framework (or MIA) has been proposed in Verimag [1, 2]. This framework can be used to compute the WCRT of a given program, for a given hardware platform. Currently, it supports platforms based on standard features (e.g., single-level round-robin arbitration, L1 cache, . . . ), as well as two generations of the MPPA ([Massively Parallel Processor Array](http://www.kalrayinc.com), a many-core processor from the Kalray company). The MPPA platforms exhibit interesting hardware features for WCRT analysis — namely, using configurable banked memories to limit interferences — which are not always available on other platforms.
Goals of the Internship
The goal of this internship is to study the impact of adding new hardware platforms to the MIA framework, in the context of the ANR project CAOTIC (Collaborative Actions on Timing Interferences, a research project funded by the Agence Nationale de la Recherche, led by Verimag). In particular, we wish to investigate how new platforms can be adapted to the banked memory model, to ease the modeling of interferences, as well as the development of critical applications.
In consequence, the following contributions are expected:
• propose new components from the literature, that would be interesting to analyze in the context of multi-/many-core based critical-systems;
• study how to model such components in the existing framework, adapting their behavior to the analysis. A particular focus will be put on communication and memory modeling, as they are the main sources of interferences in multi-/many-core systems;
• consider how those particular components might be configured to be used in critical-systems.
Contributions are hence expected both on the theoretical aspects of the framework, and on the practical side, ideally leading to the implementation of new hardware platforms in the analysis framework.
[1] M. Schuh, Implantation sûre d’applications temps-réel critiques sur plateforme pluri-coeur. PhD thesis, Université Grenoble Alpes, 2022. Available at [https://theses.hal.science/tel-03827333](https://theses.hal.science/tel-03827333).
[2] H. Rihani, Analyse temporelle des systèmes temps-réels sur architectures pluri-coeurs. PhD thesis, Université Grenoble Alpes, 2017. Available at [https://theses.hal.science/tel-01875711](https://theses.hal.science/tel-01875711).
Any older topic below may be discussed also.
Cache analysis
Advisers: David Monniaux, Claire Maïza
In order to prove bounds on the execution time of programs, it is useful to know if memory accesses are in-cache or out of cache. One can do this by static analysis. Obviously, static analysis cannot always conclude (whether an access is in cache may depend on the execution path etc.) but one wants to reduce the cases where one cannot conclude.
For caches with LRU (least recently used) replacement policies, good analysis methods are known. The goal of the internship (which may lead into a PhD) is to look at other policies.
Advanced cache analyzes
Advisers: David Monniaux, Claire Maïza
In order to bound the worst-case execution time (WCET) of programs, or to detect possible side-channel information leaks (security issue), it is necessary to statically analyze their behavior on the memory cache hierarchy.
The topic of the internship is the design and implementation of improved cache analyzes.
Exploration of timing anomaly impact on processor execution for critical real-time systems
Advisers: Lionel Rieg, Claire Maiza