@phdthesis{Mai08,
title = { Modeliser la prediction de branchement pour le calcul de temps d'execution pire-cas },
author = {Maiza-Burgui\`ere, Claire},
month = {june},
year = {2008},
school = {Universite Paul Sabatier - Toulouse 3},
team = {IRIT-TRACES},
}
Home > Verimag > Publications
bibtex
Browsing
News
New publications
- Some Recent Publications
- Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes: Self-stabilizing synchronous unison in directed networks
- Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes: On Self-stabilizing Leader Election in Directed Networks
- Léo Gourdin: Lazy Code Transformations in a Formally Verified Compiler
- Bruno Ferres, Oussama Oulkaid, Ludovic Henrio, Mehdi Khosravian, Matthieu Moy, Gabriel Radanne, Pascal Raymond: Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory
Jobs and internships
- Jobs and internships
- [Master] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
- PERSYVAL Master 2 Scholarships
- Junior professorship chair on verifiable / explainable artificial intelligence
- [Funded PhD/PostDoc] Countermeasures to (transient) Side-Channel Attacks in a Formally Verified Compiler
- [Funded PhD] Annotations de sécurité pour compilateur optimisant formellement vérifié
- [Funded PhD] Quantitative analysis of software security against adaptive attacks
- [Master] Analyzing fault parameters triggering timing anomalies
- [Master] Exploration by model-checking of timing anomaly cancellation in a processor
- [Master] Formal Methods for the Verification of Self-Adapting Distributed Systems
- [Master] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
- [Master]Leakage in presence of an active and adaptive adversary
- [PostDoc] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences