@phdthesis{Bou13a,
title = { Rigorous Design Flow for Programming Manycore Platforms },
author = {Bourgos, Paraskevas},
month = {apr},
year = {2013},
school = {Universit\'{e} de Grenoble},
team = {DCS},
}
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- Cybersécurité, sûreté et programmation Poste de Professeur⋅e des Universités Verimag/UGA
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- Marius Bozga, Radu Iosif, Arnaud Sangnier, Neven Villani: Counting Abstraction and Decidability for the Verification of Structured Parameterized Networks
- Iulia Dragomir, Carlos Redondo, Tiago Jorge, Laura Gouveia, Iulian Ober, Marius Bozga, Maxime Perrotin: Specification and model-checking of space systems in the TASTE toolset
- Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian: Modeling Techniques for the Formal Verification of Integrated Circuits at Transistor-Level: Performance vs. Precision Trade-offs
- Bruno Ferres, Oussama Oulkaid, Matthieu Moy, Gabriel Radanne, Ludovic Henrio, Pascal Raymond, Mehdi Khosravian: A Survey on Transistor-Level Electrical Rule Checking of Integrated Circuits
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- Poste de Professeur⋅e des Universités Verimag/UGA
- [PostDoc] Implementation of critical applications on multi-core: execution mode analysis to reduce interferences
- [Thèse] Contre-mesures logicielles “flot de données” pour la sécurité de bout-en-bout