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Overview
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MATLAB/Simulink to BIP
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C to BIP
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DOL to BIP
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Distribution
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System Requirements
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Installing the Toolchain
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Coding guidelines for process
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Running an example
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Case Studies
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Case Studies
MJPEG Decoder
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Actualités
Séminaires
Séminaires
14 novembre 2024
Lisa Maile:
Real-time communication with dynamic network traffic using time-sensitive networking
21 novembre 2024
Chao Huang:
Safe reinforcement learning with verification in the loss
28 novembre 2024
Grégoire Bussone:
Tba (synchronous language compilers: translation validation and optimizations)
2 décembre 2024
Thomas Vigouroux:
Analyses quantitatives pour les attaquants adaptatifs (Phd)
12 décembre 2024
Lucas Bueri:
Tba (Phd)
Nouvelles publications
Quelques Publications Récentes
Marius Bozga, Radu Iosif, Joseph Sifakis:
Verification of component-based systems with recursive architectures
Léo Gourdin:
Lazy Code Transformations in a Formally Verified Compiler
Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes:
Self-stabilizing synchronous unison in directed networks
Florence Maraninchi:
Revisiting "Good" Software Design Principles To Shape Undone Computer Science Topics
Offres d'emploi et stages
Offres d'emploi et stages
[Master] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
Bourses PERSYVAL de M2
[Funded PhD] Annotations de sécurité pour compilateur optimisant formellement vérifié
[Funded PhD] Quantitative analysis of software security against adaptive attacks
[Master] Adapting Hardware Platforms to a Multi-Core Response Time Analysis Framework
[Master] Analyzing fault parameters triggering timing anomalies
[Master] Exploration by model-checking of timing anomaly cancellation in a processor
[Master] Towards New Frontiers in Multi-Core Response Time Analysis ?
[Master]Leakage in presence of an active and adaptive adversary
[PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
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