Funded PhD position 2013-2016 available: transaction-level modeling, systems-on-a-chip, component-based design and modeling, performance properties of hardware/software systems

An Open Phd Position (2013-2016) at the Synchrone group at VERIMAG, Grenoble

Keywords: transaction-level modeling, systems-on-a-chip, component-based design and modeling, performance properties of hardware/software systems

Short Description: In the framework of a recently started European CATRENE project, the synchrone group at VERIMAG is looking for candidates for a 3-year Phd scholarship starting October 2013. The salary is 1713 Euros per month, medical insurance included. The candidate will be supervised by F. Maraninchi, leader of the group. The candidate will work in cooperation with STMicrolectronics and the other academic and indutrial partners of the project (including TU Eindhoven, Synopsys NL, ...).

The Synchrone group at VERIMAG has been working in close cooperation with STMicroelectronics since 2002 (already 4 co-supervized PhD students graduated). The general topic of the collaboration is transaction-level modeling for systems-on-a-chip, considering functional, timing and energy consumption properties. The language SystemC is the standard of the domain, and the transaction-level modeling principles (TLM) are now normalized. See related publications.

In the context of the project, we propose the following topic: high-level hierarchical component-based models for functional and non-functional (timing, energy) properties of systems-on-a-chip. High-level meaning higher than SystemC/TLM here. We will keep in mind that the models have to be interoperable with existing SystemC/TLM components, and that the models should be executable. The candidate will benefit from the availability of realistic case-studies provided by the industrial partners; he/she will also start from a well developed set of tools and approaches.

Candidates should hold a master’s degree and have a solid background in computer science and computer engineering, including hardware design. Knowledge of French is not a pre-requisite.

Expected skills: the candidate should have a background on a significant number of topics in the following list:

  • Hardware design
  • Discrete-event simulation
  • C++, SystemC/TLM
  • Component-based design, either for software, or for hardware
  • Formal models for concurrency (automata, dataflow models, ...)

Moreover, the candidate should be interested in working with academic and industrial partners, with case-studies.

Grenoble: The Grenoble area is one of Europe’s largest concentrations of academic/industrial research, hardware/software and embedded systems being one of the very strong topics.

VERIMAG,, is one of the world-wide leading academic labs in verification and model-based design of embedded systems. Its past contributions include model checking (J. Sifakis, Turing Award 2007), the data-flow language Lustre underlying the SCADE programming environment for safety-critical systems (which is the background of the Synchrone group), as well as pioneering contributions to the study of timed and hybrid systems and its applications.

Application process:

Send a motivation letter, transcripts of your master diploma, and recommendation letters from previous advizors (all these documents in pdf) to:

Please include [OpenES PhD] in the subject of your email.

We will consider applications until August 2013. Feel free to contact us if you need more details on the topic or context of the PhD.