Job Offer with Phd Thesis: Switching Reduction in Digital Circuits
Supervisors: Oded Maler, CNRS-VERIMAG, Grenoble Fahim Rahim, ATRENTA Ltd, Grenoble
Summary: a joint industry-academia thesis on a topic of which is very important for the design of mobile devices and is also interesting from algorithmic and theoretical perspectives. The candidate will be an employee of ATRENTA (2000-2500 Euro/month depending on qualifications, with a perspective of recruitment after the thesis) and will conduct his research at VERIMAG, a leading research laboratory in verification and embedded systems.
The Topic: The problem of reducing power consumption in computers in general and in mobile devices in particular is a major problem in electronic system design. For mobile devices such as smart phones, reducing consumption increases battery life and autonomy. The energy consumption of a processor is related to the number of gate switchings that it performs. It had been observed that many of these transitions are redundant and do not influence the logical behavior of the machine. The goal of the thesis is to find methods to identify transition redundancy in synthesized circuits as a first step toward transforming them into circuit which are logically equivalent but energetically more efficient. The candidate is expected to study the foundations of the problem such as minimization of Boolean functions and sequential machines and develop new algorithms for minimization and behavior-preserving circuit transformations. The candidate will apply these techniques to real designs provided by ATRENTA clients and make first steps toward integrating them in a commercial tool chain.
The thesis will be part of the French CIFRE program (pending approval) where the candidate is employed for 3-years by the company with a competitive salary. The candidate will spend his/her time evenly between VERIMAG and ATRENTA (both in Grenoble) depending on the relative intensity of theoretical and practical work at each period. The PhD title will be from the University of Grenoble in Computer Science (informatique).
Candidate Quality: We are looking for motivated candidates with excellent theoretical as well as practical skills. In particular we require knowledge in the basics of computer science and digital circuits design such as Boolean functions, automata and formal languages, algorithms, complexity, compilation and formal verification. The candidate should be an efficient programmer. Knowledge of French is advantageous but does not constitute a pre-requisite.
Send application (CV + motivation letter) to Oded.Maler@imag.fr and fahim@atrenta.com
VERIMAG , http://www-verimag.imag.fr is one of the world-wide leading academic labs in verification and model-based design of embedded systems. Its past contributions include model checking (J. Sifakis, Turing Award 2007), the data-flow language Lustre underlying the SCADE programming environment for safety-critical systems, as well as pioneering contributions to the study of timed and hybrid systems and its applications.
ATRENTA is one of the largest private electronic design automation companies with over 170 customers, including 18 of the top 20 semiconductor and consumer electronics companies. Through its SpyGlass(r) and GenSys(r) products, ATRENTA provides SoC (System on Chip) realization solutions that improves the process of going from design to fabrication. These tools deliver higher quality chips, predictable design coherence, automated chip assembly and improved implementation readiness. ATRENTA’s GuideWare reference methodologies open the way for broader deployment of system on chip (SoC) devices in the marketplace, improving time to market, reducing implementation costs and lowering risk. The work will be conducted in the recently opened R&D center of ATRENTA in Grenoble.
