@phdthesis{Moy14a,
title = { High-level Models for Embedded Systems },
author = {Moy, Matthieu},
year = {2014},
address = {Verimag},
type = {Habilitation \`a Diriger des Recherches ({HDR})},
school = {Univ. Grenoble Alpes, VERIMAG, F-38000 Grenoble, France},
team = {SYNC},
}
bibtex
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Actualités
Séminaires
Nouvelles publications
- Quelques Publications
Récentes
- Léo Gourdin, Benjamin Bonneau, Sylvain Boulmé, David Monniaux, Alexandre Bérard: Formally Verifying Optimizations with Block Simulations
- Gaëlle Walgenwitz, Benjamin Wack: Retour d'expérience -- modélisation par des automates d'un objet concret, le flexagone
- Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian, Ludovic Henrio, Gabriel Radanne: A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving
- Erwan Jahier, Karine Altisen, Stéphane Devismes: Exploring Worst Cases of Self-stabilizing Algorithms using Simulations
Offres d'emploi et stages
- Offres d'emploi et stages
- [Master] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
- Bourses PERSYVAL de M2
- Junior professorship chair on verifiable / explainable artificial intelligence
- [Funded PhD/PostDoc] Countermeasures to (transient) Side-Channel Attacks in a Formally Verified Compiler
- [Funded PhD] Annotations de sécurité pour compilateur optimisant formellement vérifié
- [Funded PhD] Quantitative analysis of software security against adaptive attacks
- [Master] Analyzing fault parameters triggering timing anomalies
- [Master] Exploration by model-checking of timing anomaly cancellation in a processor
- [Master] Formal Methods for the Verification of Self-Adapting Distributed Systems
- [Master] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
- [Master]Leakage in presence of an active and adaptive adversary
- [PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences