@phdthesis{Mai08,
title = { Modeliser la prediction de branchement pour le calcul de temps d'execution pire-cas },
author = {Maiza-Burgui\`ere, Claire},
month = {june},
year = {2008},
school = {Universite Paul Sabatier - Toulouse 3},
team = {IRIT-TRACES},
}
bibtex
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Actualités
- Séminaires
- 16 mai 2024 Gaiyun Liu: Modeling, analysis, and supervisory control of networked discrete event systems
- 30 mai 2024 Mohamed Maghenem: A hybrid-systems framework for distributed gradient-based estimation
- 27 juin 2024 Nicolas Chappe: Tba (toward a verified compilation infrastructure for concurrent programs)
Séminaires
Nouvelles publications
- Quelques Publications
Récentes
- Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes: Self-stabilizing synchronous unison in directed networks
- David Monniaux, Sylvain Boulmé: Chamois: agile development of CompCert extensions for optimization and security
- Karine Altisen, Alain Cournier, Geoffrey Defalque, Stéphane Devismes: Self-stabilizing Synchronous Unison in Directed Networks
- Karine Altisen, Stéphane Devismes, Anaïs Durand, Colette Johnen, Franck Petit: Self-stabilizing Systems in Spite of High Dynamics
Offres d'emploi et stages
- Offres d'emploi et stages
- [Master] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences
- Bourses PERSYVAL de M2
- [Funded PhD/PostDoc] Countermeasures to (transient) Side-Channel Attacks in a Formally Verified Compiler
- [Funded PhD] Annotations de sécurité pour compilateur optimisant formellement vérifié
- [Funded PhD] Quantitative analysis of software security against adaptive attacks
- [Master] Analyzing fault parameters triggering timing anomalies
- [Master] Exploration by model-checking of timing anomaly cancellation in a processor
- [Master] Formal Methods for the Verification of Self-Adapting Distributed Systems
- [Master] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
- [Master]Leakage in presence of an active and adaptive adversary
- [PostDoc] Implementation of critical applications on multi-core : execution mode analysis to reduce interferences