raymond
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Argosim and Verimag in ``La Lettre Innovation du CNRS’’
Sunday 15 September 2019
KALRAY
Saturday 31 December 2022
W-SEPT
Saturday 31 December 2016
[Master 2R 2012-2013] Semantic analysis for worst-case execution time analysis
Friday 1 March 2013
[Master] Modular Analysis for Formal Verification of Integrated Circuits at Transistor Level
Friday 1 November 2024
[PostDoc] Enhancing WCET Estimation by Exploiting Program Semantics
Friday 1 March 2013
[PostDoc] Exploiting High-Level Design Information in WCET Estimation
Friday 1 March 2013
