In the domain of security, verification is generally declined as robustness criteria and must be led against attacker models. We propose tools and technics dedicated to the evaluation of secure devices (smartcard or secured dongle) against fault attacks (such as laser or electromagnetic attacks). We are also interested for modeling and verifying other security requirements (confidentiality, integrity, isolation...) in particular in the context of Common Criteria certification.
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New publications
- Recent Publications
- Dejan Nickovic, Olivier Lebeltel, Oded Maler, Thomas Ferrére, Dogan Ulus: AMT 2.0: Qualitative and Quantitative Trace Analysis with Extended Signal Temporal Logic
- Klaus Havelund, Doron Peled, Dogan Ulus: First order temporal logic monitoring with BDDs
- Alexandre Rocca, Victor Magron, Thao Dang: Certified Roundoff Error Bounds Using Bernstein Expansions and Sparse Krivine-Stengle Representations
- Ajoy Kumar Datta, Stéphane Devismes, Lawrence L. Larmore: A Silent Self-Stabilizing Algorithm for the Generalized Minimal k-Dominating Set Problem
- Karine Altisen, Pierre Corbineau, Stéphane Devismes: A Framework for Certified Self-Stabilization
- Remy Boutonnet, Nicolas Halbwachs: Improving the results of program analysis by abstract interpretation beyond the decreasing sequence
Jobs and internships
- Jobs and internships
- Phd Position: Vulnerability search in Industrial Control Systems
- Phd Proposal : Inférence de modèles de faute pour simulation d’attaques sur composants sécurisés
- Phd proposal : Optimisation de l’évaluation et des tests de sécurité des systèmes cyber-physiques par analyse des canaux auxiliaires
- PHD proposal: Data Mining Dynamic Behaviors using Signal Temporal Logic
- Post-Doc and/or Research Engineer positions on Software Security
- [M1 internship] Modeling of Graph Topologies Using Coq
