High-confidence validation
of analog and mixed-signal circuits



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  • January 18, 2007, Kick-off meeting, at Inria Rhône-Alpes.
    • Circuit simulation using the non-smooth approach, presented by Pascal Denoyelle. Slides
    • Overview of SICONOS platform and summary of the non-smooth approach, presented by Vincent Acary. Slides1   Slides2
    • Discussion on circuit equation generation and optimization
  • March 2, 2007. Meeting at Verimag
    • Test coverage for continuous and hybrid systems, presented by Thao Dang, Slides
    • Discussion on translating a circuit description language to the input language of the SICONOS platform
  • April 17, 2007. Meeting at Inria
    • Behavioral metrics and application for circuit validation, presented by Antoine Girard, Slides
    • Discussion on extraction of circuit equations from a Spice netlist description
    • Discussion on an intermediate circuit description format using Simulink
  • June 12, 2007, VERIMAG 
    • Summary of the results obtained and preparation of the semestrial report

  • June 28, 2007, Inria Rhône-Alpes
    • Demonstration of the SINOCOS platform
    • Discussions on tool integration
  • November 7, 2007, Paris
    • Presentation of the VAL-AMS project at Colloque STIC 2007, by Antoine Girard, Slides
  • November 15, 2007, Verimag
    • Talk “Formulation of Circuit equations”, given by Olivier Bonnefon (BIPOP, Inria), Slides
    • Discussion on extraction of circuit equations from SPICE-NG
  • December 6, 2007, Verimag
    • Talk “Approximately Bisimilar Symbolic Models for Incrementally Stable Switched Systems“, by Antoine Girard (LJK). Slides
    • Talk “Using disparity to enhance testing coverage“, by Thao Dang (VERIMAG), Slides
  • May 7, 2008, Verimag
    • Talk “Verification of dynamical systems based on simulation techniques“, by Gang Zheng (LJK). Slides
  • May 25, 2008, Verimag
    • Définition des activités dans l'annee 2009
      Limitations posées par le syntaxe de SPICE pour spécifier des circuits avec des non-déterminismes utilisés pour la génération de tests.
  • Nov 25, 2008, Verimag
    • Définition des interfaces entre l'outil ACEF et l'outil de génération de tests
  • May 7, 2009, Verimag
    • Talk “Simulation analogique des circuits électriques non-réliers“, by Olivier Bonnefon (INRIA).
    • Discussion de la définition des entrées non-éterministes en utilisant le syntaxe de SPICE.
    • Discussion de la connexion entre HTG et ACEF pour spécifier les modifications entrées dans chaque pas de simulation.
  • May 10, 2009, Verimag
    • Exprimentation with the tool integrating HTG and ACEF/SICONOS