The purpose of this project is to establish a framework and a set of recommendations for the design of timing-critical software systems on cached multi-cores. The primary challenges to address are time-critical system programming and probabilistic execution time dependencies in cached platforms.
The programming of time-critical systems is challenging due to lack of consolidation in this field. Firstly, there is no consensus on how to select and program various real-time scheduling policies, especially for multiprocessor platforms and when assuming interactive run-time management of resources. There are also numerous alternatives in programming models for parallel systems with timing constraints, such as synchronous languages and the languages related to Kahn process networks. Worse still, there is a big semantical gap between the programming languages and the scheduling policies. Our goal is to address the consolidation challenges by translation to a common expressive backbone language, based on timed automata modelling approach. It should provide programmable choice of scheduling policy and model of computation as well as means to close the semantical gap between them. We will demonstrate the proof of concept in the context of ESA open-source system design framework TASTE. In this proof of concept, we will demonstrate the usability of the backbone language to design multi-processor TASTE applications and to realize state-of-the-art scheduling policies which combine multi-processor and mixed-criticality aspects, a challenging combination rarely addressed in practice.
Systems with bus and cache hierarchies are characterized by wide variations in the software execution times. For time-critical systems this signifies a challenge in the analysis of worst-case execution times. From practice it is known that extremely high execution time values are events that occur with extremely low probability, therefore probabilistic analysis is an important direction of timing-critical systems research. We seek the ways to quantify and bound the execution times and their probabilities for space-domain applications on running cached multi-cores. The two main pillars in our approach are timing analysis of the cache/bus hierarchies and the statistical analysis. The goal of the former is quantify the sources of execution time variability in common hardware architectures. The goal of the latter is to leverage the power of statistical analysis to evaluate the probabilistic dependencies of the execution times.
Partners: ITI-CERTH, Cobham (Aeroflex) Gaisler, Deimos-Space S.L.U
Verimag people involved: Petro Poplavko, Dario Socci, Saddek Bensalem, Marius Bozga
- D. Socci, P. Poplavko, S. Bensalem, M. Bozga Time-Triggered Mixed-Critical Scheduler on Single- and Multi-processor Platforms Verimag Tech. Rep. TR-2015-8, Grenoble, France, August, 2015.