Verimag

Experienced engineer wanted (compiler frontend / GUIs)

positions within the ERC STATOR project

The ERC project “STATOR” (2012-2017) focuses on discovering new algorithms for automatic proofs of program properties through static analysis. Techniques under consideration include combinations of abstract interpretation, automated theorem proving, and operation research.

The project considers both theoretical advances and practical validation of these advances on real-world software.

The engineer will develop software, test cases, and documentation. In particular, he will have primary responsibility for the implementation of the static analysis toolkit to be developed within the project.

Applicants must have a master’s degree or PhD in computer science or engineering and must be able to demonstrate their ability to conduct a significant software development project. Prior experience, especially in the area of compilers or related tools, is highly desirable.

Research will take place at the VERIMAG laboratory in Grenoble, France. VERIMAG is a joint research laboratory of Université Joseph Fourier (UJF) and CNRS, a national research organization. The engineer will be employee of UJF and enjoy associated benefits (unemployment, retirement and health, etc.) in addition to his or her salary.

Work terms up to 3 years are possible.

Starting date: as soon the project is officially started (projected date: November 1, 2012) or later dates.

If interested, please send a CV, research statement, and the names of three references with their email addresses to Dr David Monniaux <David.Monniaux> , senior researcher at CNRS, and principal investigator of the project.


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